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reuse the original data structure of repackdc and add constraint type ignore_net

This commit is contained in:
ubuntu 2023-12-05 02:00:00 -08:00
parent f7965e69aa
commit 6a1f3a1d99
5 changed files with 81 additions and 6 deletions
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6
libs/libpcf/src/base/repack_design_constraints.h
View File

@ -36,7 +36,11 @@ constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN";
*******************************************************************/
class RepackDesignConstraints {
public: /* Type of design constraints */
enum e_design_constraint_type { PIN_ASSIGNMENT, NUM_DESIGN_CONSTRAINT_TYPES };
enum e_design_constraint_type {
PIN_ASSIGNMENT,
NUM_DESIGN_CONSTRAINT_TYPES,
IGNORE_NET
};
public: /* Types */
typedef vtr::vector<RepackDesignConstraintId,

54
libs/libpcf/src/io/read_xml_repack_design_constraints.cpp
View File

@ -11,6 +11,7 @@
/* Headers from vtr util library */
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* Headers from libopenfpga util library */
@ -52,6 +53,48 @@ static void read_xml_pin_constraint(
get_attribute(xml_pin_constraint, "net", loc_data).as_string());
}
static void read_xml_ignore_net_constraint(
pugi::xml_node& xml_pin_constraint, const pugiutil::loc_data& loc_data,
RepackDesignConstraints& repack_design_constraints) {
/* Create a new design constraint in the storage */
RepackDesignConstraintId design_constraint_id =
repack_design_constraints.create_design_constraint(
RepackDesignConstraints::IGNORE_NET);
if (false == repack_design_constraints.valid_design_constraint_id(
design_constraint_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
"Fail to create design constraint!\n");
}
std::string pin_ctx_to_parse =
get_attribute(xml_pin_constraint, "pin", loc_data).as_string();
openfpga::StringToken pin_tokenizer(pin_ctx_to_parse);
std::vector<std::string> pin_info = pin_tokenizer.split('.');
/* Expect two contents, otherwise error out */
if (pin_info.size() != 2) {
std::string err_msg =
std::string("Invalid content '") + pin_ctx_to_parse +
std::string("' to skip, expect <pb_type_name>.<pin>\n");
VTR_LOG_ERROR(err_msg.c_str());
VTR_ASSERT(pin_info.size() == 2);
}
std::string pb_type_name = pin_info[0];
openfpga::PortParser port_parser(pin_info[1]);
openfpga::BasicPort curr_port = port_parser.port();
if (!curr_port.is_valid()) {
std::string err_msg =
std::string("Invalid pin definition '") + pin_ctx_to_parse +
std::string("', expect <pb_type_name>.<pin_name>[int:int]\n");
VTR_LOG_ERROR(err_msg.c_str());
VTR_ASSERT(curr_port.is_valid());
}
repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name);
repack_design_constraints.set_pin(design_constraint_id, curr_port);
repack_design_constraints.set_net(
design_constraint_id,
get_attribute(xml_pin_constraint, "name", loc_data).as_string());
}
/********************************************************************
* Parse XML codes about <repack_design_constraints> to an object of
*RepackDesignConstraints
@ -80,11 +123,16 @@ RepackDesignConstraints read_xml_repack_design_constraints(
for (pugi::xml_node xml_design_constraint : xml_root.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_design_constraint.name() != std::string("pin_constraint")) {
bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"});
}
if (xml_design_constraint.name() == std::string("pin_constraint")) {
read_xml_pin_constraint(xml_design_constraint, loc_data,
repack_design_constraints);
} else if (xml_design_constraint.name() ==
std::string("ignore_net")) {
read_xml_ignore_net_constraint(xml_design_constraint, loc_data,
repack_design_constraints);
} else {
bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"});
}
}
} catch (pugiutil::XmlError& e) {
archfpga_throw(design_constraint_fname, e.line(), "%s", e.what());

6
openfpga/src/repack/repack.cpp
View File

@ -575,10 +575,12 @@ static void add_lb_router_nets(
/* Only for global net which should be ignored, cache the sink nodes */
BasicPort curr_pin(std::string(source_pb_pin->port->name),
source_pb_pin->pin_number, source_pb_pin->pin_number);
if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) &&
if (((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) &&
(clustering_ctx.clb_nlist.net_is_global(cluster_net_id)) &&
(options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name),
curr_pin))) {
curr_pin))) ||(options.net_is_specified_to_be_ignored(
atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]),
std::string(lb_type->pb_type->name), curr_pin))) {
/* Find the net mapped to this pin in clustering results*/
AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin];

18
openfpga/src/repack/repack_option.cpp
View File

@ -46,6 +46,24 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name,
return false;
}
bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name,
std::string pb_type_name,
const BasicPort& pin) const {
const RepackDesignConstraints& design_constraint = design_constraints();
/* If found a constraint, record the net name */
for (const RepackDesignConstraintId id_ :
design_constraint.design_constraints()) {
if (design_constraint.type(id_) == RepackDesignConstraints::IGNORE_NET &&
design_constraint.pb_type(id_) == pb_type_name &&
design_constraint.net(id_) == cluster_net_name) {
if (design_constraint.pin(id_).mergeable(pin) &&
design_constraint.pin(id_).contained(pin))
return true;
}
}
return false;
}
bool RepackOption::verbose_output() const { return verbose_output_; }
/******************************************************************************

3
openfpga/src/repack/repack_option.h
View File

@ -26,6 +26,9 @@ class RepackOption {
bool is_pin_ignore_global_nets(const std::string& pb_type_name,
const BasicPort& pin) const;
bool verbose_output() const;
bool net_is_specified_to_be_ignored(
std::string cluster_net_name, std::string pb_type_name,
const BasicPort& pin) const;
public: /* Public mutators */
void set_design_constraints(