From 6a1f3a1d9988ea204c301032bb111d280ea8a6f6 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Tue, 5 Dec 2023 02:00:00 -0800 Subject: [PATCH] reuse the original data structure of repackdc and add constraint type ignore_net --- .../src/base/repack_design_constraints.h | 6 ++- .../io/read_xml_repack_design_constraints.cpp | 54 +++++++++++++++++-- openfpga/src/repack/repack.cpp | 6 ++- openfpga/src/repack/repack_option.cpp | 18 +++++++ openfpga/src/repack/repack_option.h | 3 ++ 5 files changed, 81 insertions(+), 6 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 31db9562d..2d8688baf 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -36,7 +36,11 @@ constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN"; *******************************************************************/ class RepackDesignConstraints { public: /* Type of design constraints */ - enum e_design_constraint_type { PIN_ASSIGNMENT, NUM_DESIGN_CONSTRAINT_TYPES }; + enum e_design_constraint_type { + PIN_ASSIGNMENT, + NUM_DESIGN_CONSTRAINT_TYPES, + IGNORE_NET + }; public: /* Types */ typedef vtr::vector pin_info = pin_tokenizer.split('.'); + /* Expect two contents, otherwise error out */ + if (pin_info.size() != 2) { + std::string err_msg = + std::string("Invalid content '") + pin_ctx_to_parse + + std::string("' to skip, expect .\n"); + VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(pin_info.size() == 2); + } + std::string pb_type_name = pin_info[0]; + openfpga::PortParser port_parser(pin_info[1]); + openfpga::BasicPort curr_port = port_parser.port(); + if (!curr_port.is_valid()) { + std::string err_msg = + std::string("Invalid pin definition '") + pin_ctx_to_parse + + std::string("', expect .[int:int]\n"); + VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(curr_port.is_valid()); + } + repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name); + repack_design_constraints.set_pin(design_constraint_id, curr_port); + repack_design_constraints.set_net( + design_constraint_id, + get_attribute(xml_pin_constraint, "name", loc_data).as_string()); +} /******************************************************************** * Parse XML codes about to an object of *RepackDesignConstraints @@ -80,11 +123,16 @@ RepackDesignConstraints read_xml_repack_design_constraints( for (pugi::xml_node xml_design_constraint : xml_root.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_design_constraint.name() != std::string("pin_constraint")) { + if (xml_design_constraint.name() == std::string("pin_constraint")) { + read_xml_pin_constraint(xml_design_constraint, loc_data, + repack_design_constraints); + } else if (xml_design_constraint.name() == + std::string("ignore_net")) { + read_xml_ignore_net_constraint(xml_design_constraint, loc_data, + repack_design_constraints); + } else { bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"}); } - read_xml_pin_constraint(xml_design_constraint, loc_data, - repack_design_constraints); } } catch (pugiutil::XmlError& e) { archfpga_throw(design_constraint_fname, e.line(), "%s", e.what()); diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index f80a42a41..b13fda540 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -575,10 +575,12 @@ static void add_lb_router_nets( /* Only for global net which should be ignored, cache the sink nodes */ BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); - if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) && + if (((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) && (clustering_ctx.clb_nlist.net_is_global(cluster_net_id)) && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), - curr_pin))) { + curr_pin))) ||(options.net_is_specified_to_be_ignored( + atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]), + std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index b3a06f60f..af48ae2df 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -46,6 +46,24 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, return false; } +bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, + std::string pb_type_name, + const BasicPort& pin) const { + const RepackDesignConstraints& design_constraint = design_constraints(); + /* If found a constraint, record the net name */ + for (const RepackDesignConstraintId id_ : + design_constraint.design_constraints()) { + if (design_constraint.type(id_) == RepackDesignConstraints::IGNORE_NET && + design_constraint.pb_type(id_) == pb_type_name && + design_constraint.net(id_) == cluster_net_name) { + if (design_constraint.pin(id_).mergeable(pin) && + design_constraint.pin(id_).contained(pin)) + return true; + } + } + return false; +} + bool RepackOption::verbose_output() const { return verbose_output_; } /****************************************************************************** diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h index 24f46633d..f37b6e384 100644 --- a/openfpga/src/repack/repack_option.h +++ b/openfpga/src/repack/repack_option.h @@ -26,6 +26,9 @@ class RepackOption { bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; bool verbose_output() const; + bool net_is_specified_to_be_ignored( + std::string cluster_net_name, std::string pb_type_name, + const BasicPort& pin) const; public: /* Public mutators */ void set_design_constraints(