Merge remote-tracking branch 'origin/master' into ganesh_dev
This commit is contained in:
Ganesh Gore
commit
693f3ab182
|
|
@ -1,8 +1,6 @@
|
|||
[submodule "yosys"]
|
||||
path = yosys
|
||||
url = https://github.com/YosysHQ/yosys
|
||||
branch = release-branch-0.10
|
||||
ignore = dirty
|
||||
[submodule "yosys-plugins"]
|
||||
path = yosys-plugins
|
||||
url = https://github.com/SymbiFlow/yosys-symbiflow-plugins
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou
|
|||
set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
|
||||
set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
|
||||
|
||||
#Compiler flag configuration checks
|
||||
include(CheckCXXCompilerFlag)
|
||||
|
||||
#
|
||||
# We require c++14 support
|
||||
#
|
||||
|
|
@ -218,9 +221,21 @@ endif()
|
|||
|
||||
# Set final flags
|
||||
#
|
||||
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${WARN_FLAGS} ${SANITIZE_FLAGS}")
|
||||
message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}")
|
||||
separate_arguments(
|
||||
ADDITIONAL_FLAGS UNIX_COMMAND "${SANITIZE_FLAGS} ${PROFILING_FLAGS} ${COVERAGE_FLAGS} ${LOGGING_FLAGS} ${COLORED_COMPILE} ${EXTRA_FLAGS}"
|
||||
)
|
||||
separate_arguments(
|
||||
WARN_FLAGS UNIX_COMMAND "${WARN_FLAGS}"
|
||||
)
|
||||
|
||||
#
|
||||
# Sub-projects with their own compiler settings
|
||||
#
|
||||
add_subdirectory(vtr-verilog-to-routing)
|
||||
|
||||
add_compile_options(${WARN_FLAGS}) #Add warn flags for VTR tools
|
||||
add_compile_options(${ADDITIONAL_FLAGS})
|
||||
link_libraries(${ADDITIONAL_FLAGS})
|
||||
|
||||
# Unit Testing
|
||||
#
|
||||
|
|
@ -229,9 +244,8 @@ if (OPENFPGA_WITH_TEST)
|
|||
endif()
|
||||
|
||||
#
|
||||
# Sub-projects
|
||||
# Sub-projects to apply current complier settings
|
||||
#
|
||||
add_subdirectory(vtr-verilog-to-routing)
|
||||
add_subdirectory(libs)
|
||||
add_subdirectory(openfpga)
|
||||
|
||||
|
|
@ -260,17 +274,14 @@ if (YOSYS_ENABLE_READLINE)
|
|||
find_package(Readline REQUIRED)
|
||||
endif()
|
||||
|
||||
#
|
||||
#########################
|
||||
## #
|
||||
## Compiler Flags Setup #
|
||||
## #
|
||||
#########################
|
||||
#
|
||||
## Compiler flag configuration checks
|
||||
include(CheckCCompilerFlag)
|
||||
include(CheckCXXCompilerFlag)
|
||||
#
|
||||
#PugiXml has some deliberate switch fallthrough cases (as indicated by comments), but they
|
||||
#are tagged as warnings with g++-7 (the comments don't match g++-7's suppression regexes).
|
||||
#Since we don't want to change PugiXml (it is developed externally), we relax the warning
|
||||
#level so no fallthrough warnings are generated
|
||||
CHECK_CXX_COMPILER_FLAG("-Wimplicit-fallthrough=0" CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0)
|
||||
if(CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0)
|
||||
target_compile_options(libpugixml PRIVATE "-Wimplicit-fallthrough=0")
|
||||
endif()
|
||||
|
||||
# we will check if yosys already exist. if not then build it
|
||||
if (OPENFPGA_WITH_YOSYS)
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
1.2.270
|
||||
1.2.328
|
||||
|
|
|
|||
|
|
@ -14,22 +14,22 @@ An example of the file is shown as follows.
|
|||
.. code-block:: xml
|
||||
|
||||
orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
|
||||
TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,,
|
||||
BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,,
|
||||
BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,,
|
||||
LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,,
|
||||
LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],out,,
|
||||
BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],in,,
|
||||
BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],out,,
|
||||
LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],in,,
|
||||
LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],out,,
|
||||
|
||||
An pin table may serve in various purposes. However, for OpenFPGA, the following attributes are required
|
||||
|
||||
|
|
@ -45,4 +45,8 @@ An pin table may serve in various purposes. However, for OpenFPGA, the following
|
|||
|
||||
Specify the pin name of the FPGA chip
|
||||
|
||||
.. warning:: Currently, the direction of the port is inferred by the ``port_name``. A postfix of ``A2F`` indicates an input port, while a postfix of ``F2A`` indicates an output port.
|
||||
.. option:: GPIO_type
|
||||
|
||||
Specify the pin direction. Can be [``in``|``out``].
|
||||
|
||||
.. note:: This column can be left as empty if users follow quicklogic style. See details in :ref:`openfpga_setup_commands_pcf2place`
|
||||
|
|
|
|||
|
|
@ -267,6 +267,8 @@ write_fabric_io_info
|
|||
|
||||
.. note:: This file is designed for pin constraint file conversion.
|
||||
|
||||
.. _openfpga_setup_commands_pcf2place:
|
||||
|
||||
pcf2place
|
||||
~~~~~~~~~
|
||||
|
||||
|
|
@ -292,6 +294,10 @@ pcf2place
|
|||
|
||||
Specify the path to the placement file which will be outputted by running this command
|
||||
|
||||
.. option:: --pin_table_direction_convention <string>
|
||||
|
||||
Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``.
|
||||
|
||||
.. option:: --no_time_stamp
|
||||
|
||||
Do not print time stamp in bitstream files
|
||||
|
|
|
|||
|
|
@ -60,18 +60,21 @@ bool PcfData::validate() const {
|
|||
net2pin[curr_net] = curr_pin;
|
||||
}
|
||||
/* We should not have duplicated pins in assignment: 1 pin -> 2 nets */
|
||||
std::map<BasicPort, std::string> pin2net;
|
||||
/* Caution: must use constant pointer here, otherwise you may see duplicated
|
||||
* key on BasicPort with different content! */
|
||||
std::map<const BasicPort*, std::string> pin2net;
|
||||
for (const PcfIoConstraintId& io_id : io_constraints()) {
|
||||
std::string curr_net = io_constraint_nets_[io_id];
|
||||
BasicPort curr_pin = io_constraint_pins_[io_id];
|
||||
auto result = pin2net.find(curr_pin);
|
||||
const BasicPort& curr_pin = io_constraint_pins_[io_id];
|
||||
auto result = pin2net.find(&curr_pin);
|
||||
if (result != pin2net.end()) {
|
||||
/* Found one pin assigned to two nets, this is definitely an error */
|
||||
VTR_LOG_ERROR("Pin '%s[%lu]' is assigned to two nets '%s' and '%s'!\n",
|
||||
curr_pin.get_name().c_str(), curr_pin.get_lsb(),
|
||||
result->second.c_str(), curr_net.c_str());
|
||||
num_err++;
|
||||
}
|
||||
pin2net[curr_pin] = curr_net;
|
||||
pin2net[&curr_pin] = curr_net;
|
||||
}
|
||||
if (num_err) {
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -18,10 +18,20 @@
|
|||
/* Begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
/* Constants for io pin table csv parser */
|
||||
constexpr const int ROW_INDEX_INTERNAL_PIN = 4;
|
||||
constexpr const int ROW_INDEX_EXTERNAL_PIN = 5;
|
||||
constexpr const int ROW_INDEX_DIRECTION = 6;
|
||||
constexpr const int ROW_INDEX_SIDE = 0;
|
||||
constexpr const char* DIRECTION_INPUT = "in";
|
||||
constexpr const char* DIRECTION_OUTPUT = "out";
|
||||
|
||||
/********************************************************************
|
||||
* Parse XML codes about <pin_constraints> to an object of PinConstraints
|
||||
*******************************************************************/
|
||||
IoPinTable read_csv_io_pin_table(const char* fname) {
|
||||
IoPinTable read_csv_io_pin_table(
|
||||
const char* fname,
|
||||
const e_pin_table_direction_convention& pin_dir_convention) {
|
||||
vtr::ScopedStartFinishTimer timer("Read I/O Pin Table");
|
||||
|
||||
IoPinTable io_pin_table;
|
||||
|
|
@ -40,13 +50,13 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
|
|||
std::vector<std::string> row_vec = doc.GetRow<std::string>(irow);
|
||||
IoPinTableId pin_id = io_pin_table.create_pin();
|
||||
/* Fill pin-level information */
|
||||
PortParser internal_pin_parser(row_vec.at(4));
|
||||
PortParser internal_pin_parser(row_vec.at(ROW_INDEX_INTERNAL_PIN));
|
||||
io_pin_table.set_internal_pin(pin_id, internal_pin_parser.port());
|
||||
|
||||
PortParser external_pin_parser(row_vec.at(5));
|
||||
PortParser external_pin_parser(row_vec.at(ROW_INDEX_EXTERNAL_PIN));
|
||||
io_pin_table.set_external_pin(pin_id, external_pin_parser.port());
|
||||
|
||||
std::string pin_side_str = row_vec.at(0);
|
||||
std::string pin_side_str = row_vec.at(ROW_INDEX_SIDE);
|
||||
if (side_str_map.end() == side_str_map.find(pin_side_str)) {
|
||||
VTR_LOG(
|
||||
"Invalid side defintion (='%s')! Expect [TOP|RIGHT|LEFT|BOTTOM]\n",
|
||||
|
|
@ -58,6 +68,7 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
|
|||
|
||||
/*This is not general purpose: we should have an explicit attribute in the
|
||||
* csv file to decalare direction */
|
||||
if (pin_dir_convention == e_pin_table_direction_convention::QUICKLOGIC) {
|
||||
if (internal_pin_parser.port().get_name().find("A2F") !=
|
||||
std::string::npos) {
|
||||
io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT);
|
||||
|
|
@ -71,6 +82,23 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
|
|||
}
|
||||
}
|
||||
|
||||
/* Parse pin direction from a specific column, this has a higher priority
|
||||
* than inferring from pin names */
|
||||
std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION);
|
||||
if (port_dir_str == std::string(DIRECTION_INPUT)) {
|
||||
io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT);
|
||||
} else if (port_dir_str == std::string(DIRECTION_OUTPUT)) {
|
||||
io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT);
|
||||
} else if (pin_dir_convention ==
|
||||
e_pin_table_direction_convention::EXPLICIT) {
|
||||
/* Error out only when we need explicit port direction */
|
||||
VTR_LOG(
|
||||
"Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n",
|
||||
DIRECTION_INPUT, DIRECTION_OUTPUT);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
return io_pin_table;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,21 @@
|
|||
/* Begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
IoPinTable read_csv_io_pin_table(const char* fname);
|
||||
/* Option to read csv */
|
||||
enum class e_pin_table_direction_convention {
|
||||
EXPLICIT = 0,
|
||||
QUICKLOGIC,
|
||||
NUM_TYPES
|
||||
};
|
||||
const std::map<e_pin_table_direction_convention, const char*>
|
||||
PIN_TABLE_DIRECTION_CONVENTION_STRING = {
|
||||
{e_pin_table_direction_convention::EXPLICIT, "explicit"},
|
||||
{e_pin_table_direction_convention::QUICKLOGIC,
|
||||
"quicklogic"}}; // String versions of side orientations
|
||||
|
||||
IoPinTable read_csv_io_pin_table(
|
||||
const char* fname,
|
||||
const e_pin_table_direction_convention& pin_dir_convention);
|
||||
|
||||
} /* End namespace openfpga*/
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ int main(int argc, const char** argv) {
|
|||
VTR_ASSERT((2 == argc) || (3 == argc));
|
||||
|
||||
/* Parse the fabric key from an XML file */
|
||||
openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1]);
|
||||
openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(
|
||||
argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC);
|
||||
VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]);
|
||||
|
||||
/* Output to an XML file
|
||||
|
|
|
|||
|
|
@ -42,7 +42,8 @@ int main(int argc, const char** argv) {
|
|||
openfpga::read_xml_io_location_map(argv[3]);
|
||||
VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]);
|
||||
|
||||
openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]);
|
||||
openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(
|
||||
argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC);
|
||||
VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]);
|
||||
|
||||
/* Convert */
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
|
|||
CommandOptionId opt_pin_table = cmd.option("pin_table");
|
||||
CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins");
|
||||
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
|
||||
CommandOptionId opt_pin_table_dir_convention =
|
||||
cmd.option("pin_table_direction_convention");
|
||||
CommandOptionId opt_verbose = cmd.option("verbose");
|
||||
|
||||
std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf);
|
||||
|
|
@ -45,6 +47,30 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
|
|||
std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table);
|
||||
std::string fpga_fix_pins_fname =
|
||||
cmd_context.option_value(cmd, opt_fpga_fix_pins);
|
||||
e_pin_table_direction_convention pin_table_dir_convention =
|
||||
e_pin_table_direction_convention::EXPLICIT;
|
||||
if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) {
|
||||
std::string pin_table_dir_convention_str =
|
||||
cmd_context.option_value(cmd, opt_pin_table_dir_convention);
|
||||
if (pin_table_dir_convention_str ==
|
||||
std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
|
||||
e_pin_table_direction_convention::EXPLICIT))) {
|
||||
pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT;
|
||||
} else if (pin_table_dir_convention_str ==
|
||||
std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
|
||||
e_pin_table_direction_convention::QUICKLOGIC))) {
|
||||
pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC;
|
||||
} else {
|
||||
VTR_LOG_ERROR(
|
||||
"Invalid pin naming convention ('%s') to identify port direction for "
|
||||
"pin table! Expect ['%s'|'%s'].\n",
|
||||
pin_table_dir_convention_str.c_str(),
|
||||
PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
|
||||
e_pin_table_direction_convention::EXPLICIT),
|
||||
PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
|
||||
e_pin_table_direction_convention::QUICKLOGIC));
|
||||
}
|
||||
}
|
||||
|
||||
/* Parse the input files */
|
||||
openfpga::PcfData pcf_data;
|
||||
|
|
@ -65,7 +91,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
|
|||
VTR_LOG("Read the I/O location map from an XML file: %s.\n",
|
||||
fpga_io_map_fname.c_str());
|
||||
|
||||
IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str());
|
||||
IoPinTable io_pin_table =
|
||||
read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention);
|
||||
VTR_LOG("Read the I/O pin table from a csv file: %s.\n",
|
||||
pin_table_fname.c_str());
|
||||
|
||||
|
|
|
|||
|
|
@ -528,6 +528,14 @@ static ShellCommandId add_openfpga_pcf2place_command(
|
|||
shell_cmd.set_option_require_value(opt_fpga_fix_pins_file,
|
||||
openfpga::OPT_STRING);
|
||||
|
||||
/* Add an option '--pin_table_direction_convention'*/
|
||||
CommandOptionId opt_pin_table_dir_convention =
|
||||
shell_cmd.add_option("pin_table_direction_convention", false,
|
||||
"the convention to follow when inferring pin "
|
||||
"direction from the name of ports in pin table file");
|
||||
shell_cmd.set_option_require_value(opt_pin_table_dir_convention,
|
||||
openfpga::OPT_STRING);
|
||||
|
||||
/* Add an option '--no_time_stamp' */
|
||||
shell_cmd.add_option("no_time_stamp", false,
|
||||
"Do not print time stamp in output files");
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include "build_physical_lb_rr_graph.h"
|
||||
#include "lb_router.h"
|
||||
#include "lb_router_utils.h"
|
||||
#include "pb_graph_utils.h"
|
||||
#include "pb_type_utils.h"
|
||||
#include "physical_pb_utils.h"
|
||||
#include "repack.h"
|
||||
|
|
@ -258,7 +259,10 @@ static std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(
|
|||
* This function will find the actual routing traces of the demanded net
|
||||
* There is a specific search space applied when searching the routing traces:
|
||||
* - ONLY applicable to the pb_pin of top-level pb_graph_node
|
||||
* - candidate can be limited to a set of pb pins
|
||||
* - First-tier candidates are in the same port of the source pin
|
||||
* - If nothing is found in first-tier, we find expand the range by considering
|
||||
*all the pins in the same type that are available at the top-level
|
||||
*pb_graph_node
|
||||
***************************************************************************************/
|
||||
static std::vector<int> find_pb_route_by_atom_net(
|
||||
const t_pb* pb, const t_pb_graph_pin* source_pb_pin,
|
||||
|
|
@ -267,6 +271,7 @@ static std::vector<int> find_pb_route_by_atom_net(
|
|||
|
||||
std::vector<int> pb_route_indices;
|
||||
|
||||
std::vector<int> candidate_pool;
|
||||
for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
|
||||
/* Bypass unused pins */
|
||||
if ((0 == pb->pb_route.count(pin)) ||
|
||||
|
|
@ -277,12 +282,25 @@ static std::vector<int> find_pb_route_by_atom_net(
|
|||
if (atom_net_id != pb->pb_route.at(pin).atom_net_id) {
|
||||
continue;
|
||||
}
|
||||
candidate_pool.push_back(pin);
|
||||
}
|
||||
|
||||
for (int pin : candidate_pool) {
|
||||
if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
|
||||
pb_route_indices.push_back(pin);
|
||||
}
|
||||
}
|
||||
|
||||
if (pb_route_indices.empty()) {
|
||||
for (int pin : candidate_pool) {
|
||||
if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() &&
|
||||
is_pb_graph_pins_share_interc(source_pb_pin,
|
||||
pb->pb_route.at(pin).pb_graph_pin)) {
|
||||
pb_route_indices.push_back(pin);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return pb_route_indices;
|
||||
}
|
||||
|
||||
|
|
@ -662,9 +680,16 @@ static void add_lb_router_nets(
|
|||
if (0 == pb_route_indices.size()) {
|
||||
VTR_LOGV(verbose, "Bypass routing due to no routing traces found\n");
|
||||
continue;
|
||||
} else {
|
||||
VTR_ASSERT(1 == pb_route_indices.size());
|
||||
} else if (1 == pb_route_indices.size()) {
|
||||
pb_route_index = pb_route_indices[0];
|
||||
} else {
|
||||
VTR_LOG_ERROR(
|
||||
"Found %d routing traces for net \'%s\' in clustered block \'%s\'. "
|
||||
"Expect only 1.\n",
|
||||
pb_route_indices.size(),
|
||||
atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(),
|
||||
clustering_ctx.clb_nlist.block_name(block_id).c_str());
|
||||
VTR_ASSERT(1 == pb_route_indices.size());
|
||||
}
|
||||
t_pb_graph_pin* packing_source_pb_pin =
|
||||
get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index);
|
||||
|
|
|
|||
|
|
@ -70,4 +70,34 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
|
|||
return interc;
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* This function identifies if two pb graph pins share at least one interconnect
|
||||
*model The two pins should be in the same type of port, for example, both are
|
||||
*inputs. Each pin may drive a number of outgoing edges while each edge
|
||||
*represents different interconnect model By iterating over outgoing edges for
|
||||
*each pin, common interconnect model may be found
|
||||
*******************************************************************/
|
||||
bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA,
|
||||
const t_pb_graph_pin* pinB) {
|
||||
if (pinA->port->type != pinB->port->type) {
|
||||
return false;
|
||||
}
|
||||
std::vector<t_interconnect*> pinA_interc_list;
|
||||
for (auto out_edge : pinA->output_edges) {
|
||||
if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(),
|
||||
pinA_interc_list.end(),
|
||||
out_edge->interconnect)) {
|
||||
pinA_interc_list.push_back(out_edge->interconnect);
|
||||
}
|
||||
}
|
||||
for (auto out_edge : pinB->output_edges) {
|
||||
if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(),
|
||||
pinA_interc_list.end(),
|
||||
out_edge->interconnect)) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@ std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(
|
|||
t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
|
||||
t_mode* selected_mode);
|
||||
|
||||
bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA,
|
||||
const t_pb_graph_pin* pinB);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -286,18 +286,18 @@
|
|||
of the input/output of the 32x32 multiplier
|
||||
-->
|
||||
<pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[two_mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="01" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:7]" physical_mode_pin_rotate_offset="8"/>
|
||||
<port name="b" physical_mode_port="b[0:7]" physical_mode_pin_rotate_offset="8"/>
|
||||
<port name="out" physical_mode_port="out[0:15]" physical_mode_pin_rotate_offset="16"/>
|
||||
<port name="a" physical_mode_port="a[0:7]" physical_mode_port_rotate_offset="8"/>
|
||||
<port name="b" physical_mode_port="b[0:7]" physical_mode_port_rotate_offset="8"/>
|
||||
<port name="out" physical_mode_port="out[0:15]" physical_mode_port_rotate_offset="16"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 16x16 multiplier to the physical 32x32 multiplier
|
||||
There are two 16x16 multipliers, each of which occupies part
|
||||
of the input/output of the 32x32 multiplier
|
||||
-->
|
||||
<pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[mult_16x16].mult_16x16_slice.mult_16x16" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="10" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:15]" physical_mode_pin_rotate_offset="16"/>
|
||||
<port name="b" physical_mode_port="b[0:15]" physical_mode_pin_rotate_offset="16"/>
|
||||
<port name="out" physical_mode_port="out[0:31]" physical_mode_pin_rotate_offset="32"/>
|
||||
<port name="a" physical_mode_port="a[0:15]" physical_mode_port_rotate_offset="16"/>
|
||||
<port name="b" physical_mode_port="b[0:15]" physical_mode_port_rotate_offset="16"/>
|
||||
<port name="out" physical_mode_port="out[0:31]" physical_mode_port_rotate_offset="32"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block dsp -->
|
||||
</pb_type_annotations>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,267 @@
|
|||
<?xml version="1.0"?>
|
||||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 10, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="S" size="1"/>
|
||||
<port type="input" prefix="selb" lib_name="SI" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
|
||||
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
|
||||
<!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<tile_annotations>
|
||||
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
|
||||
<tile name="clb" port="clk"/>
|
||||
<tile name="io" port="clk"/>
|
||||
</global_port>
|
||||
<global_port name="op_reset" is_reset="true" default_val="0">
|
||||
<tile name="clb" port="reset"/>
|
||||
<tile name="io" port="reset"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[physical].ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<pb_type name="io[outpad_registered].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<pb_type name="io[outpad_registered].ff[latch].latch" physical_pb_type_name="io[physical].ff" mode_bits="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="io[outpad_registered].ff[dff].dff" physical_pb_type_name="io[physical].ff" mode_bits="0"/>
|
||||
<pb_type name="io[outpad_registered].ff[dffr].dffr" physical_pb_type_name="io[physical].ff" mode_bits="0"/>
|
||||
<pb_type name="io[outpad_registered].ff[dffrn].dffrn" physical_pb_type_name="io[physical].ff" mode_bits="1">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="clk" physical_mode_port="C"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
|
||||
<port name="RN" physical_mode_port="R"/>
|
||||
</pb_type>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -298,18 +298,18 @@
|
|||
of the input/output of the 36x36 multiplier
|
||||
-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="a" physical_mode_port="a[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="b" physical_mode_port="b[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||
<port name="out" physical_mode_port="out[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
|
||||
There are two 18x18 multipliers, each of which occupies part
|
||||
of the input/output of the 36x36 multiplier
|
||||
-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
|
||||
<port name="a" physical_mode_port="a[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
<port name="b" physical_mode_port="b[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||
<port name="out" physical_mode_port="out[0:35]" physical_mode_port_rotate_offset="36"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block dsp -->
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
|
|
|
|||
|
|
@ -161,11 +161,15 @@ module frac_mem_32k (
|
|||
end else if (4'b0111 == mode) begin
|
||||
if (we_a) begin
|
||||
ram_a[addr_a[0:9]] <= data_a;
|
||||
ram_b[addr_b[0:9]] <= data_b;
|
||||
q_a <= data_a;
|
||||
q_b <= data_b;
|
||||
end else begin
|
||||
q_a <= ram_a[addr_a[0:9]];
|
||||
end
|
||||
|
||||
if (we_b) begin
|
||||
ram_b[addr_b[0:9]] <= data_b;
|
||||
q_b <= data_b;
|
||||
end else begin
|
||||
q_b <= ram_b[addr_b[0:9]];
|
||||
end
|
||||
// Operating mode: dual port RAM 2048 x 16
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
//----------------------------------------------------------------------------
|
||||
// Design Name : frac_mult_36x36
|
||||
// File Name : frac_mult_36x36.v
|
||||
// Function : A 36-bit multiplier which form from 9-bit multipliers.
|
||||
// It can operate in 3 fracturable modes:
|
||||
// 1. one 36-bit multiplier : mode[0] == 0, mode[1] == 0
|
||||
// 2. two 18-bit multipliers : mode[0] == 1, mode[1] == 0
|
||||
// 3. four 9-bit multipliers : mode[0] == 1, mode[1] == 1
|
||||
// Coder : mustafaarslan0
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
module frac_mult_36x36
|
||||
(
|
||||
input wire [0:35] a,
|
||||
input wire [0:35] b,
|
||||
output wire [0:71] out,
|
||||
input wire [0:1] mode
|
||||
);
|
||||
|
||||
wire [0:35] mult_ll_out;
|
||||
wire [0:35] mult_lh_out;
|
||||
wire [0:35] mult_hl_out;
|
||||
wire [0:35] mult_hh_out;
|
||||
|
||||
wire [0:36] sub_result1; // carry included
|
||||
wire [0:35] sub_result2;
|
||||
wire [0:71] result;
|
||||
|
||||
assign sub_result1 = mult_lh_out + mult_hl_out + {18'd0, mult_ll_out[0:17]};
|
||||
assign sub_result2 = mult_hh_out + {17'd0, sub_result1[0:18]};
|
||||
|
||||
assign result[54:71] = mult_ll_out[18:35];
|
||||
assign result[36:53] = sub_result1[19:36];
|
||||
assign result[0:35] = sub_result2;
|
||||
|
||||
assign out[36:71] = (mode[0] == 1'b1) ? mult_ll_out : result[36:71];
|
||||
assign out[0:35] = (mode[0] == 1'b1) ? mult_hh_out : result[0:35];
|
||||
|
||||
frac_mult_18x18 mult_ll (.a(a[18:35]), .b(b[18:35]), .out(mult_ll_out), .mode(mode[1]) ); // A_low*B_low
|
||||
frac_mult_18x18 mult_lh (.a(a[18:35]), .b(b[0:17]), .out(mult_lh_out), .mode(1'b0) ); // A_low*B_high
|
||||
frac_mult_18x18 mult_hl (.a(a[0:17]), .b(b[18:35]), .out(mult_hl_out), .mode(1'b0) ); // A_high*B_low
|
||||
frac_mult_18x18 mult_hh (.a(a[0:17]), .b(b[0:17]), .out(mult_hh_out), .mode(mode[1])); // A_high*B_high
|
||||
|
||||
endmodule
|
||||
|
||||
module frac_mult_18x18
|
||||
(
|
||||
input wire [0:17] a,
|
||||
input wire [0:17] b,
|
||||
output wire [0:35] out,
|
||||
input wire [0:0] mode
|
||||
);
|
||||
|
||||
wire [0:17] mult_ll_out;
|
||||
wire [0:17] mult_lh_out;
|
||||
wire [0:17] mult_hl_out;
|
||||
wire [0:17] mult_hh_out;
|
||||
|
||||
wire [0:18] sub_result1; // carry included
|
||||
wire [0:17] sub_result2;
|
||||
wire [0:35] result;
|
||||
|
||||
assign sub_result1 = mult_lh_out + mult_hl_out + {9'd0, mult_ll_out[0:8]};
|
||||
assign sub_result2 = mult_hh_out + {8'd0, sub_result1[0:9]};
|
||||
|
||||
assign result[27:35] = mult_ll_out[9:17];
|
||||
assign result[18:26] = sub_result1[10:18];
|
||||
assign result[0:17] = sub_result2;
|
||||
|
||||
assign out[18:35] = (mode == 1'b1) ? mult_ll_out : result[18:35];
|
||||
assign out[0:17] = (mode == 1'b1) ? mult_hh_out : result[0:17];
|
||||
|
||||
multiplier #(9) mult_ll (.a(a[9:17]), .b(b[9:17]), .out(mult_ll_out) ); // A_low*B_low
|
||||
multiplier #(9) mult_lh (.a(a[9:17]), .b(b[0:8]), .out(mult_lh_out) ); // A_low*B_high
|
||||
multiplier #(9) mult_hl (.a(a[0:8]), .b(b[9:17]), .out(mult_hl_out) ); // A_high*B_low
|
||||
multiplier #(9) mult_hh (.a(a[0:8]), .b(b[0:8]), .out(mult_hh_out) ); // A_high*B_high
|
||||
|
||||
endmodule
|
||||
|
||||
module multiplier
|
||||
#( parameter WIDTH = 9 )
|
||||
(
|
||||
input wire [0:WIDTH-1] a,
|
||||
input wire [0:WIDTH-1] b,
|
||||
output wire [0:2*WIDTH-1] out
|
||||
);
|
||||
|
||||
assign out = a * b;
|
||||
|
||||
endmodule
|
||||
|
|
@ -30,7 +30,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
|||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack --ignore_global_nets_on_pins clb.I[0:11] #--verbose
|
||||
repack --ignore_global_nets_on_pins clb.I[0:11] --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINT_FILE} #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# Convert .pcf to a .place file that VPR can accept
|
||||
pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE}
|
||||
pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
|
||||
|
||||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@
|
|||
run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@
|
||||
echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs";
|
||||
run-task basic_tests/k4_series/k4n4_rstOnLut $@
|
||||
run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@
|
||||
|
||||
echo -e "Testing different tile organizations";
|
||||
echo -e "Testing tiles with pins only on top and left sides";
|
||||
|
|
@ -184,8 +185,10 @@ run-task basic_tests/bus_group/full_testbench_explicit_mapping $@
|
|||
run-task basic_tests/bus_group/full_testbench_implicit_mapping $@
|
||||
|
||||
echo -e "Testing fix pins features";
|
||||
run-task basic_tests/fix_pins $@
|
||||
run-task basic_tests/constrain_pin_location $@
|
||||
run-task basic_tests/io_constraints/fix_pins $@
|
||||
run-task basic_tests/io_constraints/example_pcf $@
|
||||
run-task basic_tests/io_constraints/empty_pcf $@
|
||||
run-task basic_tests/io_constraints/pcf_ql_style $@
|
||||
|
||||
echo -e "Testing project templates";
|
||||
run-task template_tasks/vpr_blif_template $@
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
# Intended to be empt
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
|
||||
TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
|
||||
BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
|
||||
BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
|
||||
LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
|
||||
LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
|
||||
|
|
|
@ -21,10 +21,11 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
|
|||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=4x4
|
||||
openfpga_vpr_route_chan_width=20
|
||||
openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
|
||||
openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml
|
||||
openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
|
||||
openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
|
||||
openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
|
||||
openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
|
||||
openfpga_vpr_fix_pins_file=and2_fix_pins.place
|
||||
openfpga_pin_table_direction_convention=explicit
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<io_coordinates>
|
||||
<io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
|
||||
<io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
|
||||
</io_coordinates>
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
|
||||
TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
|
||||
TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
|
||||
TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
|
||||
RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
|
||||
RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
|
||||
BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
|
||||
BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
|
||||
LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
|
||||
LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
|
||||
|
|
|
@ -0,0 +1,42 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=4x4
|
||||
openfpga_vpr_route_chan_width=20
|
||||
openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
|
||||
openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
|
||||
openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
|
||||
openfpga_vpr_fix_pins_file=and2_fix_pins.place
|
||||
openfpga_pin_table_direction_convention=explicit
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_read_verilog_options_common = -nolatches
|
||||
bench0_top = and2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
|
|||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=2x2
|
||||
openfpga_vpr_route_chan_width=20
|
||||
openfpga_vpr_fix_pins_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place
|
||||
openfpga_vpr_fix_pins_file=${PATH:TASK_DIR}/config/and2_fix_pins.place
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
set_io a pad_fpga_io[0]
|
||||
set_io b pad_fpga_io[4]
|
||||
set_io c pad_fpga_io[6]
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<io_coordinates>
|
||||
<io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
|
||||
<io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
|
||||
</io_coordinates>
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=4x4
|
||||
openfpga_vpr_route_chan_width=20
|
||||
openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
|
||||
openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
|
||||
openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
|
||||
openfpga_vpr_fix_pins_file=and2_fix_pins.place
|
||||
openfpga_pin_table_direction_convention=quicklogic
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_read_verilog_options_common = -nolatches
|
||||
bench0_top = and2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
<repack_design_constraints>
|
||||
<!-- Intended to be dummy -->
|
||||
</repack_design_constraints>
|
||||
|
||||
|
|
@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
|
|||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
<pin_constraints>
|
||||
<!-- For a given .blif file, we want to assign
|
||||
- the reset signal to the op_reset[0] port of the FPGA fabric
|
||||
-->
|
||||
<set_io pin="op_reset[0]" net="rst"/>
|
||||
</pin_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
<repack_design_constraints>
|
||||
<pin_constraint pb_type="clb" pin="reset[0]" net="rst"/>
|
||||
<pin_constraint pb_type="io" pin="reset[0]" net="rst"/>
|
||||
</repack_design_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 3*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
# Yosys script parameters
|
||||
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
|
||||
bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
|
||||
bench_read_verilog_options_common = -nolatches
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
|
||||
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
|
||||
|
||||
bench0_top = rst_on_lut
|
||||
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -1,20 +1,21 @@
|
|||
mult_blocks,total_routing_area,total_routing_time,TotalRunTime,packing_time,name,io_blocks,memory_blocks,placement_time,average_net_length,routing_time,clb_blocks,critical_path,total_wire_length,total_logic_block_area
|
||||
0,8.02931,3.53,143,85.87,00_eth_top_MIN_ROUTE_CHAN_WIDTH,211,4,6.78,15.2037,3.53,292,4.34288e-09,36945,1
|
||||
0,7.23279,3.54,108,53.90,00_mc_top_MIN_ROUTE_CHAN_WIDTH,267,0,5.49,17.0883,3.54,254,7.331640000000001e-09,35800,1
|
||||
0,620306.,0.17,14,10.78,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.33,7.10949,0.17,18,2.56241e-09,974,970092
|
||||
0,5.94202,3.04,85,34.23,00_tv80s_MIN_ROUTE_CHAN_WIDTH,46,0,3.71,19.8659,3.04,202,8.90858e-09,32600,1
|
||||
0,1.13704,5.56,211,139.55,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,196,11,10.12,16.2042,5.56,414,3.8128200000000005e-09,63472,2
|
||||
0,7.23279,2.87,338,31.76,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,388,0,6.09,14.2891,2.87,267,4.37135e-09,30993,1
|
||||
0,9.51115,4.49,274,51.71,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,389,16,7.55,15.5093,4.49,343,4.749290000000001e-09,40898,2
|
||||
1,1.13704,6.18,431,91.44,00_fpu_MIN_ROUTE_CHAN_WIDTH,110,0,8.42,14.6717,6.18,429,1.6591900000000002e-07,58012,2
|
||||
0,1.13704,5.7,275,201.24,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,367,0,11.01,14.4637,5.70,424,4.54535e-09,64002,2
|
||||
0,2.10319,0.84,25,11.70,00_spi_top_MIN_ROUTE_CHAN_WIDTH,90,0,1.25,14.5174,0.84,69,5.46323e-09,7941,3
|
||||
0,4.62242,1.97,60,29.06,00_aes_MIN_ROUTE_CHAN_WIDTH,389,0,3.77,15.9033,1.97,151,5.37676e-09,21883,8
|
||||
0,8.86284,4.28,199,139.64,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,235,0,6.63,17.6241,4.28,305,5.084290000000001e-09,48290,1
|
||||
0,1.21212,86.15,694,97.52,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,2546,0,64.43,42.0125,86.15,831,5.21772e-09,258839,4
|
||||
0,789582.,0.3,10,5.62,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,33,0,0.41,7.73636,0.30,23,3.07388e-09,1702,1
|
||||
0,620306.,0.16,8,4.79,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.24,6.14844,0.16,17,1.77641e-09,787,916198
|
||||
0,417802.,0.1,4,2.35,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.14,5.20548,0.10,9,1.68994e-09,380,485046
|
||||
0,1.43501,0.49,42,31.70,00_des_MIN_ROUTE_CHAN_WIDTH,189,0,0.84,9.10709,0.49,43,3.6623500000000003e-09,5783,2
|
||||
0,620306.,0.15,6,2.75,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,33,0,0.21,6.56044,0.15,13,1.75847e-09,597,700622
|
||||
0,3.94926,1.45,78,31.64,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,431,0,2.89,13.4492,1.45,85,4.274350000000001e-09,14041,4
|
||||
name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time,name,TotalRunTime,clb_blocks,io_blocks,mult_blocks,memory_blocks,total_routing_area,total_logic_block_area,total_wire_length,packing_time,placement_time,routing_time,average_net_length,total_routing_time
|
||||
00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78,00_eth_top_MIN_ROUTE_CHAN_WIDTH,135,295,211,0,4,8.02931e+06,1.80907e+07,37792,90.64,0.00,0.78,14.8088,0.78
|
||||
00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96,00_mc_top_MIN_ROUTE_CHAN_WIDTH,107,281,267,0,0,8.02931e+06,1.51442e+07,36985,58.95,0.00,0.96,17.2023,0.96
|
||||
00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,12,19,28,0,0,620306,1.02399e+06,1028,9.21,0.00,0.04,7.84733,0.04
|
||||
00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83,00_tv80s_MIN_ROUTE_CHAN_WIDTH,85,194,46,0,0,5.26319e+06,1.04554e+07,29425,39.15,0.00,0.83,19.2951,0.83
|
||||
00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33
|
||||
00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63
|
||||
00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72
|
||||
00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23
|
||||
00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25,00_spi_top_MIN_ROUTE_CHAN_WIDTH,32,77,90,0,0,2.58198e+06,4.14984e+06,8514,17.30,0.00,0.25,15.1765,0.25
|
||||
00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72,00_aes_MIN_ROUTE_CHAN_WIDTH,64,159,389,0,0,4.62242e+06,8.56915e+06,22327,36.84,0.00,0.72,15.5480,0.72
|
||||
00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,167,308,235,0,0,8.86284e+06,1.65994e+07,45260,123.71,0.00,0.86,17.0471,0.86
|
||||
00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,399,834,2546,0,0,1.21212e+08,4.4948e+07,257039,81.13,0.02,7.08,41.6595,7.08
|
||||
00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24,00_des_MIN_ROUTE_CHAN_WIDTH,32,52,190,0,0,1.79835e+06,2.80249e+06,5936,20.26,0.00,0.24,16.2630,0.24
|
||||
00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51,00_des_MIN_ROUTE_CHAN_WIDTH,78,201,186,0,0,5.94202e+06,1.08327e+07,28710,41.72,0.00,0.51,11.5209,0.51
|
||||
00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,13,26,33,0,0,1.11081e+06,1.40124e+06,2100,7.46,0.00,0.08,8.93617,0.08
|
||||
00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,8,17,28,0,0,620306,916198,752,4.82,0.00,0.03,5.87500,0.03
|
||||
00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,5,9,28,0,0,417802,485046,295,2.44,0.00,0.02,4.04110,0.02
|
||||
00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16,00_des_MIN_ROUTE_CHAN_WIDTH,44,42,189,0,0,1.43501e+06,2.26355e+06,5746,36.12,0.00,0.16,9.06309,0.16
|
||||
00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03
|
||||
00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32
|
||||
|
|
|
|||
|
|
|
@ -39,20 +39,18 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.
|
|||
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v
|
||||
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v
|
||||
# AES core has two top modules that can be tested: encryption and decryption
|
||||
# Synthesis is too long; skip it
|
||||
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
|
||||
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v
|
||||
# FIXME: Yosys 0.22 has issues: ABC got stuck due to a lot of combinational loops. Bring this back when there is a new version
|
||||
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v
|
||||
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v
|
||||
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v
|
||||
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v
|
||||
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v
|
||||
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v
|
||||
## DES has two versions: area-optimized and performance optimized
|
||||
# The DES has same top-level module name as systemcdes
|
||||
# Currently openfpga flow has a bug which does not allow same top-level module name
|
||||
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
|
||||
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
|
||||
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
|
||||
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
|
||||
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v
|
||||
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v
|
||||
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v
|
||||
|
|
@ -85,13 +83,11 @@ bench11_top = spi_top
|
|||
bench12_top = aes
|
||||
bench13_top = usbf_top
|
||||
bench14_top = wb_conmax_top
|
||||
# Not sure either des or des3 is the top module. Need further investigation
|
||||
bench15_top = des
|
||||
bench16_top = des3
|
||||
bench16_top = des
|
||||
bench17_top = i2c_master_top
|
||||
bench18_top = sasc_top
|
||||
bench19_top = pcm_slv_top
|
||||
# May conflict with the top module name with other 'des' benchmark; This is a bug of openfpga flow scripts
|
||||
bench20_top = des
|
||||
bench21_top = usb_phy
|
||||
bench22_top = wb_dma_top
|
||||
|
|
|
|||
|
|
@ -0,0 +1,738 @@
|
|||
<?xml version="1.0"?>
|
||||
<!--
|
||||
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
|
||||
|
||||
- 40 nm technology
|
||||
- General purpose logic block:
|
||||
K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
|
||||
with optionally registered outputs
|
||||
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||
|
||||
Authors: Xifan Tang
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="frac_lut4">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut3_out"/>
|
||||
<port name="lut4_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dff">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dffr">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="R" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dffrn">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="RN" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<tile name="io" area="0">
|
||||
<sub_tile name="io" capacity="8">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad io.clk io.reset</loc>
|
||||
<loc side="top">io.outpad io.inpad io.clk io.reset</loc>
|
||||
<loc side="right">io.outpad io.inpad io.clk io.reset</loc>
|
||||
<loc side="bottom">io.outpad io.inpad io.clk io.reset</loc>
|
||||
</pinlocations>
|
||||
</sub_tile>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<sub_tile name="clb">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<pinlocations pattern="spread"/>
|
||||
</sub_tile>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="4x4" width="6" height="6">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="48x48" width="50" height="50">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="reset" num_pins="1"/>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="ff.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clk" input="io.clk" output="ff.C"/>
|
||||
<direct name="reset" input="io.reset" output="ff.R"/>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
<direct name="out2ff" input="io.outpad" output="ff.D"/>
|
||||
<mux name="mux1" input="io.outpad ff.Q" output="iopad.outpad">
|
||||
<delay_constant max="4.5e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
<delay_constant max="4.243e-11" in_port="ff.Q" out_port="iopad.outpad"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad_registered">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D">
|
||||
<pack_pattern name="registered_io" in_port="ff.D" out_port="dffr.D"/>
|
||||
</direct>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q">
|
||||
<pack_pattern name="registered_io" in_port="dffr.Q" out_port="ff.Q"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clk" input="io.clk" output="ff.C"/>
|
||||
<direct name="rst" input="io.reset" output="ff.R"/>
|
||||
<direct name="outpad" input="io.outpad" output="ff.D">
|
||||
<pack_pattern name="registered_io" in_port="io.outpad" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="ff2outpad" input="ff.Q" output="outpad.outpad">
|
||||
<pack_pattern name="registered_io" in_port="ff.Q" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<!-- Place I/Os on the sides of the FPGA -->
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||
assume, but note that the total routing area really includes the crossbar, which would push
|
||||
routing area up significantly, we estimate into the ~70% range.
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Describe fracturable logic element.
|
||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||
The outputs of the fracturable logic element can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="4">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="lut3_out" num_pins="2"/>
|
||||
<output name="lut4_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
|
||||
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
|
||||
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="ff.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
|
||||
<complete name="direct3" input="fabric.clk" output="ff[1:0].C"/>
|
||||
<complete name="direct4" input="fabric.reset" output="ff[1:0].R"/>
|
||||
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="fabric.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="fabric.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- Dual 3-LUT mode definition begin -->
|
||||
<mode name="n2_lut3">
|
||||
<pb_type name="lut3inter" num_pb="1">
|
||||
<input name="in" num_pins="3"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ble3" num_pb="2">
|
||||
<input name="in" num_pins="3"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define the LUT -->
|
||||
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="3" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
|
||||
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble3.clk" output="ff[0:0].C"/>
|
||||
<direct name="direct4" input="ble3.reset" output="ff[0:0].R"/>
|
||||
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
|
||||
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
|
||||
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
|
||||
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
|
||||
<complete name="complete2" input="lut3inter.reset" output="ble3[1:0].reset"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
|
||||
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="lut3inter.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Dual 3-LUT mode definition end -->
|
||||
<!-- 4-LUT mode definition begin -->
|
||||
<mode name="n1_lut4">
|
||||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.C"/>
|
||||
<direct name="direct4" input="ble4.reset" output="ff.R"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="ble4.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 6-LUT mode definition end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||
The delays below come from Stratix IV. the delay through a connection block
|
||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||
delay within the crossbar is 95 ps.
|
||||
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[3:0].out clb.reset" output="fle[3:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I clb.reset" out_port="fle[3:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||
</complete>
|
||||
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
|
||||
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
|
||||
</interconnect>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- Place this general purpose logic block in any unspecified column -->
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
2
yosys
2
yosys
|
|
@ -1 +1 @@
|
|||
Subproject commit dca8fb54aa625f1600e2ccb16f9763c6abfa798f
|
||||
Subproject commit f109fa3d4c56fe33bc626c298e04d45ae510dd0e
|
||||
|
|
@ -1 +1 @@
|
|||
Subproject commit 27208ce08200a5e89e3bd4f466bc68824df38c32
|
||||
Subproject commit e4d820f63c01fff5dcff5508a1ff8fe83df1cac1
|
||||
Loading…
Reference in New Issue