From c45b51a31996d5fd90719ae8fc44036a3f576d58 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 12 Oct 2022 06:19:46 +0000 Subject: [PATCH 01/43] Bump yosys-plugins from `27208ce` to `b3430d2` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `27208ce` to `b3430d2`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/27208ce08200a5e89e3bd4f466bc68824df38c32...b3430d2e55181ab12ea67396a59c753fd342bbbc) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 27208ce08..b3430d2e5 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 27208ce08200a5e89e3bd4f466bc68824df38c32 +Subproject commit b3430d2e55181ab12ea67396a59c753fd342bbbc From f62d435b1ea7c7e568fe0755b40dce6151808ae0 Mon Sep 17 00:00:00 2001 From: Yunus Emre ERYILMAZ <30428379+yunuseryilmaz18@users.noreply.github.com> Date: Wed, 12 Oct 2022 09:35:35 +0300 Subject: [PATCH 02/43] Update frac_mem_32k.v --- .../openfpga_cell_library/verilog/frac_mem_32k.v | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v index 2d0b8fd26..b99753e7f 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v @@ -161,13 +161,17 @@ module frac_mem_32k ( end else if (4'b0111 == mode) begin if (we_a) begin ram_a[addr_a[0:9]] <= data_a; - ram_b[addr_b[0:9]] <= data_b; q_a <= data_a; - q_b <= data_b; end else begin q_a <= ram_a[addr_a[0:9]]; + end + + if (we_b) begin + ram_b[addr_b[0:9]] <= data_b; + q_b <= data_b; + end else begin q_b <= ram_b[addr_b[0:9]]; - end + end // Operating mode: dual port RAM 2048 x 16 end else if (4'b1000 == mode) begin if (we_a) begin From 6f55371d4b73299f4fc368f0b54a47dbe1e4d0d7 Mon Sep 17 00:00:00 2001 From: "mustafa.arslan" Date: Thu, 13 Oct 2022 13:53:32 +0300 Subject: [PATCH 03/43] Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset". --- ...em32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml index dc39b625c..1997ab1f3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml @@ -298,18 +298,18 @@ of the input/output of the 36x36 multiplier --> - - - + + + - - - + + + From d7a253408d741b9581f5897e306c1936cd1f89c3 Mon Sep 17 00:00:00 2001 From: "mustafa.arslan" Date: Thu, 13 Oct 2022 14:00:59 +0300 Subject: [PATCH 04/43] Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset". --- ...er_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index bd350e389..0fcbfba3f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -286,18 +286,18 @@ of the input/output of the 32x32 multiplier --> - - - + + + - - - + + + From 7f67794787f63d209fa41d087b11366343928267 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 10:54:40 -0700 Subject: [PATCH 05/43] [arch]add new arch to test --- ...lobal_nets_on_pins_example_script.openfpga | 2 +- .../config/pin_constraints_reset.xml | 7 + .../k4n4_rstOnLut_strong/config/task.conf | 43 + ...e_fracff_rstOnLut_registerable_io_40nm.xml | 735 ++++++++++++++++++ 4 files changed, 786 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml diff --git a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga index 9fff5a5d9..315816d04 100644 --- a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga @@ -30,7 +30,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack --ignore_global_nets_on_pins clb.I[0:11] #--verbose +repack --ignore_global_nets_on_pins clb.I[0:11] --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINT_FILE} #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml new file mode 100644 index 000000000..317f88671 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf new file mode 100644 index 000000000..61c992d3a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml new file mode 100644 index 000000000..bd1ca8181 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml @@ -0,0 +1,735 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7b7217d116c68500623d162ca0c2dc019937a49b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:08:51 -0700 Subject: [PATCH 06/43] [arch]add new arch to test --- ...racff_40nm_registerable_io_cc_openfpga.xml | 266 ++++++++++++++++++ 1 file changed, 266 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..3282f29db --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -0,0 +1,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 5cf315958d63ccaae83b0d7fa21971b2c172451d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:17:34 -0700 Subject: [PATCH 07/43] [test] deploy new test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 288b8a277..47d7067f7 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -134,6 +134,7 @@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; run-task basic_tests/k4_series/k4n4_rstOnLut $@ +run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; From b0be27b384e8963cf15c4ae1bde6be4193876544 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:22:48 -0700 Subject: [PATCH 08/43] [test] add repack design constraints files --- .../k4n4_rstOnLut/config/repack_design_constraints.xml | 4 ++++ .../basic_tests/k4_series/k4n4_rstOnLut/config/task.conf | 1 + .../config/repack_design_constraints.xml | 5 +++++ 3 files changed, 10 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf index ba2269805..dd6574e18 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml new file mode 100644 index 000000000..9ed626423 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml @@ -0,0 +1,5 @@ + + + + + From 32f48f16c72339705882294276646aee12a44858 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:54:58 -0700 Subject: [PATCH 09/43] [arch] fixed a few bugs --- ...eable_fracff_rstOnLut_registerable_io_40nm.xml | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml index bd1ca8181..049874bba 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml @@ -238,9 +238,6 @@ - - - @@ -324,10 +321,14 @@ - + + + - + + + @@ -354,7 +355,9 @@ - + + + From 1c36ac28f19bc1784a740bda3652515d8e054222 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 12:17:32 -0700 Subject: [PATCH 10/43] [arch] code format --- .../k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml index 3282f29db..8a05bacc2 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -223,7 +223,6 @@ - From 31da9bf6eacf0524bd2b08597eeefcfc1a532c74 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 15:10:25 -0700 Subject: [PATCH 11/43] [engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node --- openfpga/src/repack/repack.cpp | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 33c27937b..577dd00cd 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -258,7 +258,8 @@ static std::vector find_routed_pb_graph_pins_atom_net( * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: * - ONLY applicable to the pb_pin of top-level pb_graph_node - * - candidate can be limited to a set of pb pins + * - First-tier candidates are in the same port of the source pin + * - If nothing is found in first-tier, we find expand the range by considering all the pins in the same type that are available at the top-level pb_graph_node ***************************************************************************************/ static std::vector find_pb_route_by_atom_net( const t_pb* pb, const t_pb_graph_pin* source_pb_pin, @@ -267,6 +268,7 @@ static std::vector find_pb_route_by_atom_net( std::vector pb_route_indices; + std::vector candidate_pool; for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { /* Bypass unused pins */ if ((0 == pb->pb_route.count(pin)) || @@ -277,12 +279,23 @@ static std::vector find_pb_route_by_atom_net( if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { continue; } + candidate_pool.push_back(pin); + } + for (int pin : candidate_pool) { if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { pb_route_indices.push_back(pin); } } + if (pb_route_indices.empty()) { + for (int pin : candidate_pool) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && source_pb_pin->port->type == pb->pb_route.at(pin).pb_graph_pin->port->type) { + pb_route_indices.push_back(pin); + } + } + } + return pb_route_indices; } @@ -662,9 +675,12 @@ static void add_lb_router_nets( if (0 == pb_route_indices.size()) { VTR_LOGV(verbose, "Bypass routing due to no routing traces found\n"); continue; - } else { - VTR_ASSERT(1 == pb_route_indices.size()); + } else if (1 == pb_route_indices.size()) { pb_route_index = pb_route_indices[0]; + } else { + VTR_LOG_ERROR("Found %d routing traces for net \'%s\' in clustered block \'%s\'. Expect only 1.\n", + pb_route_indices.size(), atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), clustering_ctx.clb_nlist.block_name(block_id).c_str()); + VTR_ASSERT(1 == pb_route_indices.size()); } t_pb_graph_pin* packing_source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index); From 33e2b16cb1ca40384c1f66cab4978bf57f2b19ef Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 15:33:43 -0700 Subject: [PATCH 12/43] [arch] fixed a bug which caused verification failed --- .../k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml index 8a05bacc2..c2f043af5 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -202,9 +202,11 @@ + + From d1f3338837ef9bf9985b953da2dbd736d98f84b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 16:26:45 -0700 Subject: [PATCH 13/43] [engine] now repacker find only routable pins when given a net to search routing traces --- openfpga/src/repack/repack.cpp | 3 ++- openfpga/src/utils/pb_graph_utils.cpp | 24 ++++++++++++++++++++++++ openfpga/src/utils/pb_graph_utils.h | 2 ++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 577dd00cd..562a41f44 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -11,6 +11,7 @@ #include "build_physical_lb_rr_graph.h" #include "lb_router.h" #include "lb_router_utils.h" +#include "pb_graph_utils.h" #include "pb_type_utils.h" #include "physical_pb_utils.h" #include "repack.h" @@ -290,7 +291,7 @@ static std::vector find_pb_route_by_atom_net( if (pb_route_indices.empty()) { for (int pin : candidate_pool) { - if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && source_pb_pin->port->type == pb->pb_route.at(pin).pb_graph_pin->port->type) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && is_pb_graph_pins_share_interc(source_pb_pin, pb->pb_route.at(pin).pb_graph_pin)) { pb_route_indices.push_back(pin); } } diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp index 4b80bd596..4746535fd 100644 --- a/openfpga/src/utils/pb_graph_utils.cpp +++ b/openfpga/src/utils/pb_graph_utils.cpp @@ -70,4 +70,28 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, return interc; } +/******************************************************************** + * This function identifies if two pb graph pins share at least one interconnect model + * The two pins should be in the same type of port, for example, both are inputs. + * Each pin may drive a number of outgoing edges while each edge represents different interconnect model + * By iterating over outgoing edges for each pin, common interconnect model may be found + *******************************************************************/ +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB) { + if (pinA->port->type != pinB->port->type) { + return false; + } + std::vector pinA_interc_list; + for (auto out_edge : pinA->output_edges) { + if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + pinA_interc_list.push_back(out_edge->interconnect); + } + } + for (auto out_edge : pinB->output_edges) { + if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + return true; + } + } + return false; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h index 209f87b9f..cbe2a096d 100644 --- a/openfpga/src/utils/pb_graph_utils.h +++ b/openfpga/src/utils/pb_graph_utils.h @@ -22,6 +22,8 @@ std::vector pb_graph_pin_inputs( t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, t_mode* selected_mode); +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB); + } /* end namespace openfpga */ #endif From 0af6c76239b87b079ecff36b1beb02617d59bfe1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 16:27:57 -0700 Subject: [PATCH 14/43] [engine] code format --- openfpga/src/repack/repack.cpp | 18 +++++++++++++----- openfpga/src/utils/pb_graph_utils.cpp | 22 ++++++++++++++-------- openfpga/src/utils/pb_graph_utils.h | 3 ++- 3 files changed, 29 insertions(+), 14 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 562a41f44..6dcc64a70 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -259,8 +259,10 @@ static std::vector find_routed_pb_graph_pins_atom_net( * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: * - ONLY applicable to the pb_pin of top-level pb_graph_node - * - First-tier candidates are in the same port of the source pin - * - If nothing is found in first-tier, we find expand the range by considering all the pins in the same type that are available at the top-level pb_graph_node + * - First-tier candidates are in the same port of the source pin + * - If nothing is found in first-tier, we find expand the range by considering + *all the pins in the same type that are available at the top-level + *pb_graph_node ***************************************************************************************/ static std::vector find_pb_route_by_atom_net( const t_pb* pb, const t_pb_graph_pin* source_pb_pin, @@ -291,7 +293,9 @@ static std::vector find_pb_route_by_atom_net( if (pb_route_indices.empty()) { for (int pin : candidate_pool) { - if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && is_pb_graph_pins_share_interc(source_pb_pin, pb->pb_route.at(pin).pb_graph_pin)) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && + is_pb_graph_pins_share_interc(source_pb_pin, + pb->pb_route.at(pin).pb_graph_pin)) { pb_route_indices.push_back(pin); } } @@ -679,8 +683,12 @@ static void add_lb_router_nets( } else if (1 == pb_route_indices.size()) { pb_route_index = pb_route_indices[0]; } else { - VTR_LOG_ERROR("Found %d routing traces for net \'%s\' in clustered block \'%s\'. Expect only 1.\n", - pb_route_indices.size(), atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), clustering_ctx.clb_nlist.block_name(block_id).c_str()); + VTR_LOG_ERROR( + "Found %d routing traces for net \'%s\' in clustered block \'%s\'. " + "Expect only 1.\n", + pb_route_indices.size(), + atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), + clustering_ctx.clb_nlist.block_name(block_id).c_str()); VTR_ASSERT(1 == pb_route_indices.size()); } t_pb_graph_pin* packing_source_pb_pin = diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp index 4746535fd..5187bbaac 100644 --- a/openfpga/src/utils/pb_graph_utils.cpp +++ b/openfpga/src/utils/pb_graph_utils.cpp @@ -71,23 +71,29 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, } /******************************************************************** - * This function identifies if two pb graph pins share at least one interconnect model - * The two pins should be in the same type of port, for example, both are inputs. - * Each pin may drive a number of outgoing edges while each edge represents different interconnect model - * By iterating over outgoing edges for each pin, common interconnect model may be found + * This function identifies if two pb graph pins share at least one interconnect + *model The two pins should be in the same type of port, for example, both are + *inputs. Each pin may drive a number of outgoing edges while each edge + *represents different interconnect model By iterating over outgoing edges for + *each pin, common interconnect model may be found *******************************************************************/ -bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB) { +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, + const t_pb_graph_pin* pinB) { if (pinA->port->type != pinB->port->type) { return false; } std::vector pinA_interc_list; for (auto out_edge : pinA->output_edges) { - if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), + pinA_interc_list.end(), + out_edge->interconnect)) { pinA_interc_list.push_back(out_edge->interconnect); } - } + } for (auto out_edge : pinB->output_edges) { - if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), + pinA_interc_list.end(), + out_edge->interconnect)) { return true; } } diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h index cbe2a096d..e340ba860 100644 --- a/openfpga/src/utils/pb_graph_utils.h +++ b/openfpga/src/utils/pb_graph_utils.h @@ -22,7 +22,8 @@ std::vector pb_graph_pin_inputs( t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, t_mode* selected_mode); -bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB); +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, + const t_pb_graph_pin* pinB); } /* end namespace openfpga */ From 3a1c1f326ae3fc97684ee6b695e03369a9b5d743 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 14 Oct 2022 02:02:34 +0000 Subject: [PATCH 15/43] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 815cddf28..dcc45f800 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.270 +1.2.292 From aa78981e37de57fb29e9748c60ced60b5d3d3e89 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 11:18:21 -0700 Subject: [PATCH 16/43] [test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory --- .../regression_test_scripts/basic_reg_test.sh | 5 ++- .../fix_pins/config/and2_fix_pins.place | 3 -- .../io_constraints/empty_pcf/config/and2.pcf | 1 + .../empty_pcf}/config/fpga_io_location.xml | 0 .../config/pinmap_k4_N4_tileable_40nm.csv | 0 .../empty_pcf}/config/task.conf | 0 .../example_pcf}/config/and2.pcf | 0 .../example_pcf/config/fpga_io_location.xml | 18 ++++++++ .../config/pinmap_k4_N4_tileable_40nm.csv | 17 ++++++++ .../example_pcf/config/task.conf | 41 +++++++++++++++++++ .../fix_pins/config/task.conf | 0 11 files changed, 80 insertions(+), 5 deletions(-) delete mode 100644 openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/fpga_io_location.xml (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/pinmap_k4_N4_tileable_40nm.csv (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/task.conf (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/example_pcf}/config/and2.pcf (100%) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf rename openfpga_flow/tasks/basic_tests/{ => io_constraints}/fix_pins/config/task.conf (100%) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 47d7067f7..221426609 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -185,8 +185,9 @@ run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ echo -e "Testing fix pins features"; -run-task basic_tests/fix_pins $@ -run-task basic_tests/constrain_pin_location $@ +run-task basic_tests/io_constraints/fix_pins $@ +run-task basic_tests/io_constraints/example_pcf $@ +run-task basic_tests/io_constraints/empty_pcf $@ echo -e "Testing project templates"; run-task template_tasks/vpr_blif_template $@ diff --git a/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place b/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place deleted file mode 100644 index 5f24ccebe..000000000 --- a/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place +++ /dev/null @@ -1,3 +0,0 @@ -a 0 1 0 -b 2 0 3 -out:c 1 3 7 diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf new file mode 100644 index 000000000..43a5d7296 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf @@ -0,0 +1 @@ +# Intended to be empt diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/fpga_io_location.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/fpga_io_location.xml diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/and2.pcf similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf rename to openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/and2.pcf diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml new file mode 100644 index 000000000..03eb56357 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv new file mode 100644 index 000000000..ba0691940 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -0,0 +1,17 @@ +orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf new file mode 100644 index 000000000..a7d18889b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf +openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml +openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_vpr_fix_pins_file=and2_fix_pins.place + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/fix_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/fix_pins/config/task.conf rename to openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf From 8b00bfdff986c26a77724f4c0dea1fcd310f70bc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 11:55:57 -0700 Subject: [PATCH 17/43] [test] replace hardcoded paths in task config files with relative paths --- .../basic_tests/io_constraints/empty_pcf/config/task.conf | 6 +++--- .../basic_tests/io_constraints/example_pcf/config/task.conf | 6 +++--- .../basic_tests/io_constraints/fix_pins/config/task.conf | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf index a7d18889b..b16acaecc 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 openfpga_vpr_route_chan_width=20 -openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf -openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml -openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf index a7d18889b..b16acaecc 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 openfpga_vpr_route_chan_width=20 -openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf -openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml -openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf index 56fd9ff4f..3aef18436 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=20 -openfpga_vpr_fix_pins_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place +openfpga_vpr_fix_pins_file=${PATH:TASK_DIR}/config/and2_fix_pins.place [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml From dbbabbc0981dd1952c7f642f85753d5aedf9389b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 12:23:39 -0700 Subject: [PATCH 18/43] [lib] developing the support on forcing pin direction from a specific column in pin table .csv --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 26 +++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 18bc0499c..0a1e90d9c 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -18,6 +18,14 @@ /* Begin namespace openfpga */ namespace openfpga { +/* Constants for io pin table csv parser */ +constexpr const int ROW_INDEX_INTERNAL_PIN = 4; +constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; +constexpr const int ROW_INDEX_DIRECTION = 6; +constexpr const int ROW_INDEX_SIDE = 0; +constexpr const char* DIRECTION_INPUT = "in"; +constexpr const char* DIRECTION_OUTPUT = "out"; + /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ @@ -40,13 +48,13 @@ IoPinTable read_csv_io_pin_table(const char* fname) { std::vector row_vec = doc.GetRow(irow); IoPinTableId pin_id = io_pin_table.create_pin(); /* Fill pin-level information */ - PortParser internal_pin_parser(row_vec.at(4)); + PortParser internal_pin_parser(row_vec.at(ROW_INDEX_INTERNAL_PIN)); io_pin_table.set_internal_pin(pin_id, internal_pin_parser.port()); - PortParser external_pin_parser(row_vec.at(5)); + PortParser external_pin_parser(row_vec.at(ROW_INDEX_EXTERNAL_PIN)); io_pin_table.set_external_pin(pin_id, external_pin_parser.port()); - std::string pin_side_str = row_vec.at(0); + std::string pin_side_str = row_vec.at(ROW_INDEX_SIDE); if (side_str_map.end() == side_str_map.find(pin_side_str)) { VTR_LOG( "Invalid side defintion (='%s')! Expect [TOP|RIGHT|LEFT|BOTTOM]\n", @@ -69,6 +77,18 @@ IoPinTable read_csv_io_pin_table(const char* fname) { "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + + /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else { + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); + } } return io_pin_table; From 2f434fd4d31422c637f49c34d93bbe0c992cda5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 12:35:06 -0700 Subject: [PATCH 19/43] [lib] developing pin dir convention support --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 24 +++++++++++--------- libs/libpcf/src/io/read_csv_io_pin_table.h | 10 +++++++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 0a1e90d9c..8f07e1b7d 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -29,7 +29,7 @@ constexpr const char* DIRECTION_OUTPUT = "out"; /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ -IoPinTable read_csv_io_pin_table(const char* fname) { +IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention) { vtr::ScopedStartFinishTimer timer("Read I/O Pin Table"); IoPinTable io_pin_table; @@ -66,16 +66,18 @@ IoPinTable read_csv_io_pin_table(const char* fname) { /*This is not general purpose: we should have an explicit attribute in the * csv file to decalare direction */ - if (internal_pin_parser.port().get_name().find("A2F") != - std::string::npos) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (internal_pin_parser.port().get_name().find("F2A") != - std::string::npos) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else { - VTR_LOG( - "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); - exit(1); + if (pin_dir_convention == e_pin_table_direction_convention::QUICKLOGIC) { + if (internal_pin_parser.port().get_name().find("A2F") != + std::string::npos) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (internal_pin_parser.port().get_name().find("F2A") != + std::string::npos) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else { + VTR_LOG( + "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); + exit(1); + } } /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index c82b5f9cf..acf3473a5 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -14,7 +14,15 @@ /* Begin namespace openfpga */ namespace openfpga { -IoPinTable read_csv_io_pin_table(const char* fname); +/* Option to read csv */ +enum class e_pin_table_direction_convention { + EXPLICIT = 0, + QUICKLOGIC, + NUM_PIN_DIRECTION_CONVENTION +}; +constexpr std::array PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations + +IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); } /* End namespace openfpga*/ From aef94171c27183b88c21f4426c157d028a0a53c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 13:55:18 -0700 Subject: [PATCH 20/43] [doc] update options for pcf2place command --- .../openfpga_shell/openfpga_commands/setup_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 98e539044..7e84351da 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -292,6 +292,10 @@ pcf2place Specify the path to the placement file which will be outputted by running this command + .. option:: --pin_table_direction_convention + + Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``. + .. option:: --no_time_stamp Do not print time stamp in bitstream files From 11624cd0c6315ad00b2249bae1df8315095f3a41 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:08:21 -0700 Subject: [PATCH 21/43] [engine] enabling new feature: pin_table_direction_convention --- libs/libpcf/test/test_csv_io_pin_table.cpp | 2 +- libs/libpcf/test/test_pcf2place.cpp | 2 +- openfpga/src/base/openfpga_pcf2place.cpp | 15 ++++++++++++++- openfpga/src/base/openfpga_setup_command.cpp | 7 +++++++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/test/test_csv_io_pin_table.cpp b/libs/libpcf/test/test_csv_io_pin_table.cpp index 22084d6b9..b918b7775 100644 --- a/libs/libpcf/test/test_csv_io_pin_table.cpp +++ b/libs/libpcf/test/test_csv_io_pin_table.cpp @@ -16,7 +16,7 @@ int main(int argc, const char** argv) { VTR_ASSERT((2 == argc) || (3 == argc)); /* Parse the fabric key from an XML file */ - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1]); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]); /* Output to an XML file diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index 05b9614d2..b70e5339b 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -43,7 +43,7 @@ int main(int argc, const char** argv) { VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]); - VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); + VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); /* Convert */ openfpga::IoNetPlace io_net_place; diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index 02ecea463..bcb069b8b 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -36,6 +36,7 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, CommandOptionId opt_pin_table = cmd.option("pin_table"); CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_pin_table_dir_convention = cmd.option("pin_table_direction_convention"); CommandOptionId opt_verbose = cmd.option("verbose"); std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf); @@ -45,6 +46,18 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table); std::string fpga_fix_pins_fname = cmd_context.option_value(cmd, opt_fpga_fix_pins); + e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { + std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); + if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT])) { + pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC])) { + pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; + } else { + VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", + pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT], PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC]); + } + } /* Parse the input files */ openfpga::PcfData pcf_data; @@ -65,7 +78,7 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, VTR_LOG("Read the I/O location map from an XML file: %s.\n", fpga_io_map_fname.c_str()); - IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str()); + IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", pin_table_fname.c_str()); diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 50719d026..7be458bfd 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -528,6 +528,13 @@ static ShellCommandId add_openfpga_pcf2place_command( shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, openfpga::OPT_STRING); + /* Add an option '--pin_table_direction_convention'*/ + CommandOptionId opt_pin_table_dir_convention = shell_cmd.add_option( + "pin_table_direction_convention", false, + "the convention to follow when inferring pin direction from the name of ports in pin table file"); + shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, + openfpga::OPT_STRING); + /* Add an option '--no_time_stamp' */ shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files"); From 811438c20e7f4c7ac6ab30968f55aad8559f526e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:20:23 -0700 Subject: [PATCH 22/43] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index acf3473a5..50f5e3d2a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -18,9 +18,9 @@ namespace openfpga { enum class e_pin_table_direction_convention { EXPLICIT = 0, QUICKLOGIC, - NUM_PIN_DIRECTION_CONVENTION + NUM_TYPES }; -constexpr std::array PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations +constexpr std::array(e_pin_table_direction_convention::NUM_TYPES)> PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); From 63d8b00630ac1eb76dea6bb9bab9f85ad049a299 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:54:18 -0700 Subject: [PATCH 23/43] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.h | 5 ++++- libs/libpcf/test/test_pcf2place.cpp | 4 ++-- openfpga/src/base/openfpga_pcf2place.cpp | 6 +++--- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index 50f5e3d2a..e1b121bff 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -20,7 +20,10 @@ enum class e_pin_table_direction_convention { QUICKLOGIC, NUM_TYPES }; -constexpr std::array(e_pin_table_direction_convention::NUM_TYPES)> PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations +const std::map PIN_TABLE_DIRECTION_CONVENTION_STRING = { + {e_pin_table_direction_convention::EXPLICIT, "explicit"}, + {e_pin_table_direction_convention::QUICKLOGIC, "quicklogic"} +}; //String versions of side orientations IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index b70e5339b..38e1c18c4 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -42,8 +42,8 @@ int main(int argc, const char** argv) { openfpga::read_xml_io_location_map(argv[3]); VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]); - VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); /* Convert */ openfpga::IoNetPlace io_net_place; diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index bcb069b8b..215d54b3b 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -49,13 +49,13 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); - if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT])) { + if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT))) { pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; - } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC])) { + } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC))) { pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; } else { VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", - pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT], PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC]); + pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC)); } } From 0f2b8da7f01707741d8c160ee38ceafd007d090c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:55:34 -0700 Subject: [PATCH 24/43] [engine] code format --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 16 +++++++---- libs/libpcf/src/io/read_csv_io_pin_table.h | 13 +++++---- libs/libpcf/test/test_csv_io_pin_table.cpp | 3 +- libs/libpcf/test/test_pcf2place.cpp | 3 +- openfpga/src/base/openfpga_pcf2place.cpp | 30 ++++++++++++++------ openfpga/src/base/openfpga_setup_command.cpp | 7 +++-- 6 files changed, 48 insertions(+), 24 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 8f07e1b7d..a3f3f775a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -20,16 +20,18 @@ namespace openfpga { /* Constants for io pin table csv parser */ constexpr const int ROW_INDEX_INTERNAL_PIN = 4; -constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; -constexpr const int ROW_INDEX_DIRECTION = 6; -constexpr const int ROW_INDEX_SIDE = 0; +constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; +constexpr const int ROW_INDEX_DIRECTION = 6; +constexpr const int ROW_INDEX_SIDE = 0; constexpr const char* DIRECTION_INPUT = "in"; constexpr const char* DIRECTION_OUTPUT = "out"; /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ -IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention) { +IoPinTable read_csv_io_pin_table( + const char* fname, + const e_pin_table_direction_convention& pin_dir_convention) { vtr::ScopedStartFinishTimer timer("Read I/O Pin Table"); IoPinTable io_pin_table; @@ -80,7 +82,8 @@ IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_ } } - /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); if (port_dir_str == std::string(DIRECTION_INPUT)) { io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); @@ -88,7 +91,8 @@ IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_ io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); } else { VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", DIRECTION_INPUT, DIRECTION_OUTPUT); + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); exit(1); } } diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index e1b121bff..a3a7d7281 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -20,12 +20,15 @@ enum class e_pin_table_direction_convention { QUICKLOGIC, NUM_TYPES }; -const std::map PIN_TABLE_DIRECTION_CONVENTION_STRING = { - {e_pin_table_direction_convention::EXPLICIT, "explicit"}, - {e_pin_table_direction_convention::QUICKLOGIC, "quicklogic"} -}; //String versions of side orientations +const std::map + PIN_TABLE_DIRECTION_CONVENTION_STRING = { + {e_pin_table_direction_convention::EXPLICIT, "explicit"}, + {e_pin_table_direction_convention::QUICKLOGIC, + "quicklogic"}}; // String versions of side orientations -IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); +IoPinTable read_csv_io_pin_table( + const char* fname, + const e_pin_table_direction_convention& pin_dir_convention); } /* End namespace openfpga*/ diff --git a/libs/libpcf/test/test_csv_io_pin_table.cpp b/libs/libpcf/test/test_csv_io_pin_table.cpp index b918b7775..e9d51fb90 100644 --- a/libs/libpcf/test/test_csv_io_pin_table.cpp +++ b/libs/libpcf/test/test_csv_io_pin_table.cpp @@ -16,7 +16,8 @@ int main(int argc, const char** argv) { VTR_ASSERT((2 == argc) || (3 == argc)); /* Parse the fabric key from an XML file */ - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table( + argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]); /* Output to an XML file diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index 38e1c18c4..ba72651d7 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -42,7 +42,8 @@ int main(int argc, const char** argv) { openfpga::read_xml_io_location_map(argv[3]); VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table( + argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); /* Convert */ diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index 215d54b3b..c3b70e85c 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -36,7 +36,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, CommandOptionId opt_pin_table = cmd.option("pin_table"); CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); - CommandOptionId opt_pin_table_dir_convention = cmd.option("pin_table_direction_convention"); + CommandOptionId opt_pin_table_dir_convention = + cmd.option("pin_table_direction_convention"); CommandOptionId opt_verbose = cmd.option("verbose"); std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf); @@ -46,16 +47,28 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table); std::string fpga_fix_pins_fname = cmd_context.option_value(cmd, opt_fpga_fix_pins); - e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + e_pin_table_direction_convention pin_table_dir_convention = + e_pin_table_direction_convention::EXPLICIT; if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { - std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); - if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT))) { + std::string pin_table_dir_convention_str = + cmd_context.option_value(cmd, opt_pin_table_dir_convention); + if (pin_table_dir_convention_str == + std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::EXPLICIT))) { pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; - } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC))) { + } else if (pin_table_dir_convention_str == + std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::QUICKLOGIC))) { pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; } else { - VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", - pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC)); + VTR_LOG_ERROR( + "Invalid pin naming convention ('%s') to identify port direction for " + "pin table! Expect ['%s'|'%s'].\n", + pin_table_dir_convention_str.c_str(), + PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::EXPLICIT), + PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::QUICKLOGIC)); } } @@ -78,7 +91,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, VTR_LOG("Read the I/O location map from an XML file: %s.\n", fpga_io_map_fname.c_str()); - IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); + IoPinTable io_pin_table = + read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", pin_table_fname.c_str()); diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 7be458bfd..ec8252aca 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -529,9 +529,10 @@ static ShellCommandId add_openfpga_pcf2place_command( openfpga::OPT_STRING); /* Add an option '--pin_table_direction_convention'*/ - CommandOptionId opt_pin_table_dir_convention = shell_cmd.add_option( - "pin_table_direction_convention", false, - "the convention to follow when inferring pin direction from the name of ports in pin table file"); + CommandOptionId opt_pin_table_dir_convention = + shell_cmd.add_option("pin_table_direction_convention", false, + "the convention to follow when inferring pin " + "direction from the name of ports in pin table file"); shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, openfpga::OPT_STRING); From b82ebf2f231802ebeeeacb99eb6a3000c1a5dc9d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:16:23 -0700 Subject: [PATCH 25/43] [script] suppress warnings for vtr libs --- CMakeLists.txt | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9077328fc..748735ad0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -82,6 +82,9 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing") set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number") +#Compiler flag configuration checks +include(CheckCXXCompilerFlag) + # # We require c++14 support # @@ -218,9 +221,21 @@ endif() # Set final flags # -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${WARN_FLAGS} ${SANITIZE_FLAGS}") -message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}") +separate_arguments( + ADDITIONAL_FLAGS UNIX_COMMAND "${SANITIZE_FLAGS} ${PROFILING_FLAGS} ${COVERAGE_FLAGS} ${LOGGING_FLAGS} ${COLORED_COMPILE} ${EXTRA_FLAGS}" + ) +separate_arguments( + WARN_FLAGS UNIX_COMMAND "${WARN_FLAGS}" + ) +# +# Sub-projects with their own compiler settings +# +add_subdirectory(vtr-verilog-to-routing) + +add_compile_options(${WARN_FLAGS}) #Add warn flags for VTR tools +add_compile_options(${ADDITIONAL_FLAGS}) +link_libraries(${ADDITIONAL_FLAGS}) # Unit Testing # @@ -229,9 +244,8 @@ if (OPENFPGA_WITH_TEST) endif() # -# Sub-projects +# Sub-projects to apply current complier settings # -add_subdirectory(vtr-verilog-to-routing) add_subdirectory(libs) add_subdirectory(openfpga) @@ -260,17 +274,14 @@ if (YOSYS_ENABLE_READLINE) find_package(Readline REQUIRED) endif() -# -######################### -## # -## Compiler Flags Setup # -## # -######################### -# -## Compiler flag configuration checks -include(CheckCCompilerFlag) -include(CheckCXXCompilerFlag) -# +#PugiXml has some deliberate switch fallthrough cases (as indicated by comments), but they +#are tagged as warnings with g++-7 (the comments don't match g++-7's suppression regexes). +#Since we don't want to change PugiXml (it is developed externally), we relax the warning +#level so no fallthrough warnings are generated +CHECK_CXX_COMPILER_FLAG("-Wimplicit-fallthrough=0" CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0) +if(CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0) + target_compile_options(libpugixml PRIVATE "-Wimplicit-fallthrough=0") +endif() # we will check if yosys already exist. if not then build it if (OPENFPGA_WITH_YOSYS) From 609e096b1a10bd9f310024921a23eeb98abb7667 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:25:19 -0700 Subject: [PATCH 26/43] [test] added a new test to validate explicit port direction in pin table support --- .../pin_constrain_example_script.openfpga | 2 +- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/pinmap_k4_N4_tileable_40nm.csv | 32 +++++++------- .../io_constraints/empty_pcf/config/task.conf | 1 + .../config/pinmap_k4_N4_tileable_40nm.csv | 32 +++++++------- .../example_pcf/config/task.conf | 1 + .../pcf_ql_style/config/and2.pcf | 3 ++ .../pcf_ql_style/config/fpga_io_location.xml | 18 ++++++++ .../config/pinmap_k4_N4_tileable_40nm.csv | 17 ++++++++ .../pcf_ql_style/config/task.conf | 42 +++++++++++++++++++ 10 files changed, 116 insertions(+), 33 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf diff --git a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga index ad29fc51e..f25bf0323 100644 --- a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga @@ -1,5 +1,5 @@ # Convert .pcf to a .place file that VPR can accept -pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} +pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION} # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 221426609..e4bd6cff0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -188,6 +188,7 @@ echo -e "Testing fix pins features"; run-task basic_tests/io_constraints/fix_pins $@ run-task basic_tests/io_constraints/example_pcf $@ run-task basic_tests/io_constraints/empty_pcf $@ +run-task basic_tests/io_constraints/pcf_ql_style $@ echo -e "Testing project templates"; run-task template_tasks/vpr_blif_template $@ diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv index ba0691940..9b7206eba 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -1,17 +1,17 @@ orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge -TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, -TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, -RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, -RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, -BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, -BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, -LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, -LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf index b16acaecc..131d6246a 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf @@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv index ba0691940..9b7206eba 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -1,17 +1,17 @@ orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge -TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, -TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, -RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, -RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, -BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, -BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, -LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, -LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf index b16acaecc..131d6246a 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf new file mode 100644 index 000000000..839f8a857 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf @@ -0,0 +1,3 @@ +set_io a pad_fpga_io[0] +set_io b pad_fpga_io[4] +set_io c pad_fpga_io[6] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml new file mode 100644 index 000000000..03eb56357 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv new file mode 100644 index 000000000..ba0691940 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv @@ -0,0 +1,17 @@ +orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf new file mode 100644 index 000000000..cc57345e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=quicklogic + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From c4de6655b6959d491b888b26f2f4fc9aa099c7e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:26:21 -0700 Subject: [PATCH 27/43] [engine] bug --- openfpga/src/base/openfpga_setup_command.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index ec8252aca..08e9c7497 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -533,7 +533,7 @@ static ShellCommandId add_openfpga_pcf2place_command( shell_cmd.add_option("pin_table_direction_convention", false, "the convention to follow when inferring pin " "direction from the name of ports in pin table file"); - shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, + shell_cmd.set_option_require_value(opt_pin_table_dir_convention, openfpga::OPT_STRING); /* Add an option '--no_time_stamp' */ From 70b0d2e505a56b91da6c1779fcf0bcce14622d7c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:32:00 -0700 Subject: [PATCH 28/43] [doc] update pin table file format for pin direction keywords --- .../manual/file_formats/pin_table_file.rst | 38 ++++++++++--------- .../openfpga_commands/setup_commands.rst | 2 + 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/docs/source/manual/file_formats/pin_table_file.rst b/docs/source/manual/file_formats/pin_table_file.rst index 033f7c9b7..46b316e7b 100644 --- a/docs/source/manual/file_formats/pin_table_file.rst +++ b/docs/source/manual/file_formats/pin_table_file.rst @@ -14,22 +14,22 @@ An example of the file is shown as follows. .. code-block:: xml orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge - TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, - TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, - TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,, - TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,, - TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,, - TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,, - TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,, - TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,, - RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,, - RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,, - RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,, - RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,, - BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,, - BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,, - LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,, - LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,, + TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, + TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, + TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],in,, + TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],out,, + TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],in,, + TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],out,, + TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],in,, + TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],out,, + RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],in,, + RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],out,, + RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],in,, + RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],out,, + BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],in,, + BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],out,, + LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],in,, + LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],out,, An pin table may serve in various purposes. However, for OpenFPGA, the following attributes are required @@ -45,4 +45,8 @@ An pin table may serve in various purposes. However, for OpenFPGA, the following Specify the pin name of the FPGA chip -.. warning:: Currently, the direction of the port is inferred by the ``port_name``. A postfix of ``A2F`` indicates an input port, while a postfix of ``F2A`` indicates an output port. +.. option:: GPIO_type + + Specify the pin direction. Can be [``in``|``out``]. + + .. note:: This column can be left as empty if users follow quicklogic style. See details in :ref:`openfpga_setup_commands_pcf2place` diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 7e84351da..9c05ee00c 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -267,6 +267,8 @@ write_fabric_io_info .. note:: This file is designed for pin constraint file conversion. +.. _openfpga_setup_commands_pcf2place: + pcf2place ~~~~~~~~~ From c3f180372debbc34a6d0110211db7a28f27c64ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:42:22 -0700 Subject: [PATCH 29/43] [engine] do not error out when ql-style is used in pin table --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 33 ++++++++++---------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index a3f3f775a..9431ee579 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -80,24 +80,25 @@ IoPinTable read_csv_io_pin_table( "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else if (pin_dir_convention == + e_pin_table_direction_convention::EXPLICIT) { + /* Error out only when we need explicit port direction */ + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); + } } - /* Parse pin direction from a specific column, this has a higher priority - * than inferring from pin names */ - std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); - if (port_dir_str == std::string(DIRECTION_INPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else { - VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", - DIRECTION_INPUT, DIRECTION_OUTPUT); - exit(1); - } + return io_pin_table; } - return io_pin_table; -} - } /* End namespace openfpga*/ From 76862efa5703b3c4c13d44011f7007ee8207b545 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:46:19 -0700 Subject: [PATCH 30/43] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 29 ++++++++++---------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 9431ee579..1138aeb5a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -81,21 +81,20 @@ IoPinTable read_csv_io_pin_table( exit(1); } - /* Parse pin direction from a specific column, this has a higher priority - * than inferring from pin names */ - std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); - if (port_dir_str == std::string(DIRECTION_INPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else if (pin_dir_convention == - e_pin_table_direction_convention::EXPLICIT) { - /* Error out only when we need explicit port direction */ - VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", - DIRECTION_INPUT, DIRECTION_OUTPUT); - exit(1); - } + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else if (pin_dir_convention == + e_pin_table_direction_convention::EXPLICIT) { + /* Error out only when we need explicit port direction */ + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); } return io_pin_table; From 60c448c98dbf16975db4acbbcfd5b9057f7415c7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:49:34 -0700 Subject: [PATCH 31/43] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 1138aeb5a..9df012290 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -80,6 +80,7 @@ IoPinTable read_csv_io_pin_table( "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + } /* Parse pin direction from a specific column, this has a higher priority * than inferring from pin names */ From c9631497e2a2ef923df201857e341f2e16ab6f75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 16:11:49 -0700 Subject: [PATCH 32/43] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 9df012290..6c7c2cc3f 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -97,8 +97,9 @@ IoPinTable read_csv_io_pin_table( DIRECTION_INPUT, DIRECTION_OUTPUT); exit(1); } - - return io_pin_table; } + return io_pin_table; +} + } /* End namespace openfpga*/ From 00a485cbeb63f7e10331a52f3cb57011a8b2612b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 19:44:25 -0700 Subject: [PATCH 33/43] [test] add missing file --- .../io_constraints/fix_pins/config/and2_fix_pins.place | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place new file mode 100644 index 000000000..5f24ccebe --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place @@ -0,0 +1,3 @@ +a 0 1 0 +b 2 0 3 +out:c 1 3 7 From 829ebce86116f2ff6a0cb1cc30ce8e8e59a60432 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 18 Oct 2022 05:39:18 +0000 Subject: [PATCH 34/43] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index dcc45f800..36f343f81 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.292 +1.2.313 From 98fcfd4ceb285de0d50cce7aa15d4fff1e8b953b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 21 Oct 2022 06:35:23 +0000 Subject: [PATCH 35/43] Bump yosys-plugins from `b3430d2` to `e4d820f` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `b3430d2` to `e4d820f`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/b3430d2e55181ab12ea67396a59c753fd342bbbc...e4d820f63c01fff5dcff5508a1ff8fe83df1cac1) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index b3430d2e5..e4d820f63 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit b3430d2e55181ab12ea67396a59c753fd342bbbc +Subproject commit e4d820f63c01fff5dcff5508a1ff8fe83df1cac1 From db0e5dff93e5cea6cb6ea1fa072de2a001e10bf2 Mon Sep 17 00:00:00 2001 From: "mustafa.arslan" Date: Fri, 21 Oct 2022 17:30:20 +0300 Subject: [PATCH 36/43] Added new cell library for fracturable dsp36 Added new divisible 36x36 multiplier cell library for architectures which has fracturable dsp36: - The 36x36 multiplier is form from sixteen 9x9 multipliers. - It operates same modes with existing library. It can operate in 3 fracturable modes: 1. one 36-bit multiplier 2. two 18-bit multipliers 3. four 9-bit multipliers - It provides ~%20 better area than existing cell library (mult_36x36.v) Comparison made with Synopsys Design Compiler NXT: mult_36x36.v Total cell area 20470 um2 frac_mult_36x36.v Total cell area 15103 um2 --- .../verilog/frac_mult_36x36.v | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 openfpga_flow/openfpga_cell_library/verilog/frac_mult_36x36.v diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_mult_36x36.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_36x36.v new file mode 100644 index 000000000..a0d6fb7f9 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_36x36.v @@ -0,0 +1,90 @@ +//---------------------------------------------------------------------------- +// Design Name : frac_mult_36x36 +// File Name : frac_mult_36x36.v +// Function : A 36-bit multiplier which form from 9-bit multipliers. +// It can operate in 3 fracturable modes: +// 1. one 36-bit multiplier : mode[0] == 0, mode[1] == 0 +// 2. two 18-bit multipliers : mode[0] == 1, mode[1] == 0 +// 3. four 9-bit multipliers : mode[0] == 1, mode[1] == 1 +// Coder : mustafaarslan0 +//---------------------------------------------------------------------------- + +module frac_mult_36x36 +( + input wire [0:35] a, + input wire [0:35] b, + output wire [0:71] out, + input wire [0:1] mode +); + +wire [0:35] mult_ll_out; +wire [0:35] mult_lh_out; +wire [0:35] mult_hl_out; +wire [0:35] mult_hh_out; + +wire [0:36] sub_result1; // carry included +wire [0:35] sub_result2; +wire [0:71] result; + + assign sub_result1 = mult_lh_out + mult_hl_out + {18'd0, mult_ll_out[0:17]}; + assign sub_result2 = mult_hh_out + {17'd0, sub_result1[0:18]}; + + assign result[54:71] = mult_ll_out[18:35]; + assign result[36:53] = sub_result1[19:36]; + assign result[0:35] = sub_result2; + + assign out[36:71] = (mode[0] == 1'b1) ? mult_ll_out : result[36:71]; + assign out[0:35] = (mode[0] == 1'b1) ? mult_hh_out : result[0:35]; + + frac_mult_18x18 mult_ll (.a(a[18:35]), .b(b[18:35]), .out(mult_ll_out), .mode(mode[1]) ); // A_low*B_low + frac_mult_18x18 mult_lh (.a(a[18:35]), .b(b[0:17]), .out(mult_lh_out), .mode(1'b0) ); // A_low*B_high + frac_mult_18x18 mult_hl (.a(a[0:17]), .b(b[18:35]), .out(mult_hl_out), .mode(1'b0) ); // A_high*B_low + frac_mult_18x18 mult_hh (.a(a[0:17]), .b(b[0:17]), .out(mult_hh_out), .mode(mode[1])); // A_high*B_high + +endmodule + +module frac_mult_18x18 +( + input wire [0:17] a, + input wire [0:17] b, + output wire [0:35] out, + input wire [0:0] mode +); + +wire [0:17] mult_ll_out; +wire [0:17] mult_lh_out; +wire [0:17] mult_hl_out; +wire [0:17] mult_hh_out; + +wire [0:18] sub_result1; // carry included +wire [0:17] sub_result2; +wire [0:35] result; + + assign sub_result1 = mult_lh_out + mult_hl_out + {9'd0, mult_ll_out[0:8]}; + assign sub_result2 = mult_hh_out + {8'd0, sub_result1[0:9]}; + + assign result[27:35] = mult_ll_out[9:17]; + assign result[18:26] = sub_result1[10:18]; + assign result[0:17] = sub_result2; + + assign out[18:35] = (mode == 1'b1) ? mult_ll_out : result[18:35]; + assign out[0:17] = (mode == 1'b1) ? mult_hh_out : result[0:17]; + + multiplier #(9) mult_ll (.a(a[9:17]), .b(b[9:17]), .out(mult_ll_out) ); // A_low*B_low + multiplier #(9) mult_lh (.a(a[9:17]), .b(b[0:8]), .out(mult_lh_out) ); // A_low*B_high + multiplier #(9) mult_hl (.a(a[0:8]), .b(b[9:17]), .out(mult_hl_out) ); // A_high*B_low + multiplier #(9) mult_hh (.a(a[0:8]), .b(b[0:8]), .out(mult_hh_out) ); // A_high*B_high + +endmodule + +module multiplier +#( parameter WIDTH = 9 ) +( + input wire [0:WIDTH-1] a, + input wire [0:WIDTH-1] b, + output wire [0:2*WIDTH-1] out +); + + assign out = a * b; + +endmodule From b720b49eb16f569de26c645782f281d24c3b049a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 11:48:09 -0700 Subject: [PATCH 37/43] [lib] now count pcf errors --- libs/libpcf/src/base/pcf_data.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libpcf/src/base/pcf_data.cpp b/libs/libpcf/src/base/pcf_data.cpp index e4a036666..41043d04e 100644 --- a/libs/libpcf/src/base/pcf_data.cpp +++ b/libs/libpcf/src/base/pcf_data.cpp @@ -70,6 +70,7 @@ bool PcfData::validate() const { VTR_LOG_ERROR("Pin '%s[%lu]' is assigned to two nets '%s' and '%s'!\n", curr_pin.get_name().c_str(), curr_pin.get_lsb(), result->second.c_str(), curr_net.c_str()); + num_err++; } pin2net[curr_pin] = curr_net; } From 0999c9444b759beb1db21461f274593340f55b63 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 12:44:56 -0700 Subject: [PATCH 38/43] [lib] remove debugging messages --- libs/libpcf/src/base/pcf_data.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/libs/libpcf/src/base/pcf_data.cpp b/libs/libpcf/src/base/pcf_data.cpp index 41043d04e..f4505b539 100644 --- a/libs/libpcf/src/base/pcf_data.cpp +++ b/libs/libpcf/src/base/pcf_data.cpp @@ -60,11 +60,12 @@ bool PcfData::validate() const { net2pin[curr_net] = curr_pin; } /* We should not have duplicated pins in assignment: 1 pin -> 2 nets */ - std::map pin2net; + /* Caution: must use constant pointer here, otherwise you may see duplicated key on BasicPort with different content! */ + std::map pin2net; for (const PcfIoConstraintId& io_id : io_constraints()) { std::string curr_net = io_constraint_nets_[io_id]; - BasicPort curr_pin = io_constraint_pins_[io_id]; - auto result = pin2net.find(curr_pin); + const BasicPort& curr_pin = io_constraint_pins_[io_id]; + auto result = pin2net.find(&curr_pin); if (result != pin2net.end()) { /* Found one pin assigned to two nets, this is definitely an error */ VTR_LOG_ERROR("Pin '%s[%lu]' is assigned to two nets '%s' and '%s'!\n", @@ -72,7 +73,7 @@ bool PcfData::validate() const { result->second.c_str(), curr_net.c_str()); num_err++; } - pin2net[curr_pin] = curr_net; + pin2net[&curr_pin] = curr_net; } if (num_err) { return false; From 2d428269195fd4498ed689e5fae5025f22d3d396 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 13:03:03 -0700 Subject: [PATCH 39/43] [lib] code format --- libs/libpcf/src/base/pcf_data.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libs/libpcf/src/base/pcf_data.cpp b/libs/libpcf/src/base/pcf_data.cpp index f4505b539..46b624b47 100644 --- a/libs/libpcf/src/base/pcf_data.cpp +++ b/libs/libpcf/src/base/pcf_data.cpp @@ -60,7 +60,8 @@ bool PcfData::validate() const { net2pin[curr_net] = curr_pin; } /* We should not have duplicated pins in assignment: 1 pin -> 2 nets */ - /* Caution: must use constant pointer here, otherwise you may see duplicated key on BasicPort with different content! */ + /* Caution: must use constant pointer here, otherwise you may see duplicated + * key on BasicPort with different content! */ std::map pin2net; for (const PcfIoConstraintId& io_id : io_constraints()) { std::string curr_net = io_constraint_nets_[io_id]; From 57b86eaebf4f9c11ecd231daa4df1b67d86ff09b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 16:57:00 -0700 Subject: [PATCH 40/43] [yosys] update to v0.22 --- .gitmodules | 2 -- yosys | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index af518a717..5fdc702e6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,6 @@ [submodule "yosys"] path = yosys url = https://github.com/YosysHQ/yosys - branch = release-branch-0.10 - ignore = dirty [submodule "yosys-plugins"] path = yosys-plugins url = https://github.com/SymbiFlow/yosys-symbiflow-plugins diff --git a/yosys b/yosys index dca8fb54a..f109fa3d4 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit dca8fb54aa625f1600e2ccb16f9763c6abfa798f +Subproject commit f109fa3d4c56fe33bc626c298e04d45ae510dd0e From 04286508c8f2074531dae128c4901909b7af269e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 20:26:56 -0700 Subject: [PATCH 41/43] [test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back --- .../benchmark_sweep/iwls2005/config/task.conf | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf index c7f1ae148..7cd78a850 100644 --- a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf @@ -39,20 +39,18 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*. bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v # AES core has two top modules that can be tested: encryption and decryption -# Synthesis is too long; skip it bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v -bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v +# FIXME: Yosys 0.22 has issues: ABC got stuck due to a lot of combinational loops. Bring this back when there is a new version +#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v ## DES has two versions: area-optimized and performance optimized -# The DES has same top-level module name as systemcdes -# Currently openfpga flow has a bug which does not allow same top-level module name -#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v -#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v +bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v +bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v @@ -85,13 +83,11 @@ bench11_top = spi_top bench12_top = aes bench13_top = usbf_top bench14_top = wb_conmax_top -# Not sure either des or des3 is the top module. Need further investigation bench15_top = des -bench16_top = des3 +bench16_top = des bench17_top = i2c_master_top bench18_top = sasc_top bench19_top = pcm_slv_top -# May conflict with the top module name with other 'des' benchmark; This is a bug of openfpga flow scripts bench20_top = des bench21_top = usb_phy bench22_top = wb_dma_top From 40f1f2fbc63a31439718098bcdbc3c8c4e1f5642 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Oct 2022 20:28:10 -0700 Subject: [PATCH 42/43] [test] update golden results for iwls --- .../config/iwls_benchmark_golden_results.csv | 41 ++++++++++--------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv index fe07fa1c1..89659b480 100644 --- a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv @@ -1,20 +1,21 @@ -mult_blocks,total_routing_area,total_routing_time,TotalRunTime,packing_time,name,io_blocks,memory_blocks,placement_time,average_net_length,routing_time,clb_blocks,critical_path,total_wire_length,total_logic_block_area -0,8.02931,3.53,143,85.87,00_eth_top_MIN_ROUTE_CHAN_WIDTH,211,4,6.78,15.2037,3.53,292,4.34288e-09,36945,1 -0,7.23279,3.54,108,53.90,00_mc_top_MIN_ROUTE_CHAN_WIDTH,267,0,5.49,17.0883,3.54,254,7.331640000000001e-09,35800,1 -0,620306.,0.17,14,10.78,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.33,7.10949,0.17,18,2.56241e-09,974,970092 -0,5.94202,3.04,85,34.23,00_tv80s_MIN_ROUTE_CHAN_WIDTH,46,0,3.71,19.8659,3.04,202,8.90858e-09,32600,1 -0,1.13704,5.56,211,139.55,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,196,11,10.12,16.2042,5.56,414,3.8128200000000005e-09,63472,2 -0,7.23279,2.87,338,31.76,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,388,0,6.09,14.2891,2.87,267,4.37135e-09,30993,1 -0,9.51115,4.49,274,51.71,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,389,16,7.55,15.5093,4.49,343,4.749290000000001e-09,40898,2 -1,1.13704,6.18,431,91.44,00_fpu_MIN_ROUTE_CHAN_WIDTH,110,0,8.42,14.6717,6.18,429,1.6591900000000002e-07,58012,2 -0,1.13704,5.7,275,201.24,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,367,0,11.01,14.4637,5.70,424,4.54535e-09,64002,2 -0,2.10319,0.84,25,11.70,00_spi_top_MIN_ROUTE_CHAN_WIDTH,90,0,1.25,14.5174,0.84,69,5.46323e-09,7941,3 -0,4.62242,1.97,60,29.06,00_aes_MIN_ROUTE_CHAN_WIDTH,389,0,3.77,15.9033,1.97,151,5.37676e-09,21883,8 -0,8.86284,4.28,199,139.64,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,235,0,6.63,17.6241,4.28,305,5.084290000000001e-09,48290,1 -0,1.21212,86.15,694,97.52,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,2546,0,64.43,42.0125,86.15,831,5.21772e-09,258839,4 -0,789582.,0.3,10,5.62,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,33,0,0.41,7.73636,0.30,23,3.07388e-09,1702,1 -0,620306.,0.16,8,4.79,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.24,6.14844,0.16,17,1.77641e-09,787,916198 -0,417802.,0.1,4,2.35,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.14,5.20548,0.10,9,1.68994e-09,380,485046 -0,1.43501,0.49,42,31.70,00_des_MIN_ROUTE_CHAN_WIDTH,189,0,0.84,9.10709,0.49,43,3.6623500000000003e-09,5783,2 -0,620306.,0.15,6,2.75,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,33,0,0.21,6.56044,0.15,13,1.75847e-09,597,700622 -0,3.94926,1.45,78,31.64,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,431,0,2.89,13.4492,1.45,85,4.274350000000001e-09,14041,4 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+00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,198,426,196,0,11,1.13704e+07,2.89868e+07,61761,149.96,0.00,1.33,15.8809,1.33 +00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,67,155,388,0,0,4.62242e+06,8.35357e+06,20502,23.55,0.00,0.63,14.4380,0.63 +00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,99,191,389,0,16,5.26319e+06,1.90618e+07,24602,49.30,0.00,0.72,14.0103,0.72 +00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,373,435,367,0,0,1.23690e+07,2.34439e+07,63096,319.11,0.00,1.23,14.4088,1.23 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+00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,6,11,33,0,0,417802,592834,449,3.08,0.00,0.03,5.10227,0.03 +00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,83,87,431,0,0,3.94926e+06,4.68878e+06,13673,39.48,0.00,0.32,13.2619,0.32 From 9e45154f817a5625e4aea08d35cfb90170ca8b1e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 22 Oct 2022 21:28:03 +0000 Subject: [PATCH 43/43] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 36f343f81..3c69b2873 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.313 +1.2.328