add a new include netlist for all the fabric-related netlists

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -124,13 +124,17 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                            src_dir_path,
                            options.explicit_port_mapping());
 
+  /* Generate an netlist including all the fabric-related netlists */
+  print_fabric_include_netlist(const_cast<const NetlistManager&>(netlist_manager),
+                               src_dir_path,
+                               circuit_lib);
+
   /* Given a brief stats on how many Verilog modules have been written to files */
   VTR_LOGV(options.verbose_output(), 
            "Written %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }
 
-
 /********************************************************************
  * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
  * This function will generate

openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp

@@ -25,8 +25,73 @@ namespace openfpga {
  *******************************************************************/
 
 /********************************************************************
- * Print a file that includes all the netlists that have been generated
+ * Print a file that includes all the fabric netlists 
- * and user-defined.
+ * that have been generated  and user-defined.
+ * This does NOT include any testbenches!
+ * Some netlists are open to compile under specific preprocessing flags
+ *******************************************************************/
+void print_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                  const std::string& src_dir,
+                                  const CircuitLibrary& circuit_lib) {
+  std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Fabric Netlist Summary")); 
+
+  /* Print preprocessing flags */
+  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
+  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
+  fp << std::endl;
+
+  /* Include all the user-defined netlists */
+  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
+  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
+    print_verilog_include_netlist(fp, user_defined_netlist);
+  }
+
+  /* Include all the primitive modules */
+  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the CLB, heterogeneous block modules */
+  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the routing architecture modules */
+  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include FPGA top module */
+  print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Close the file stream */
+  fp.close();
+}
+
+/********************************************************************
+ * Print a file that includes all the netlists 
+ * including the fabric netlists and testbenches
+ * that have been generated and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
 void print_include_netlists(const NetlistManager& netlist_manager,

openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h

@@ -17,6 +17,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+void print_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                  const std::string& src_dir,
+                                  const CircuitLibrary& circuit_lib);
+
 void print_include_netlists(const NetlistManager& netlist_manager,
                             const std::string& src_dir,
                             const std::string& circuit_name,

openfpga/src/fpga_verilog/verilog_constants.h

@@ -22,6 +22,7 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
+constexpr char* FABRIC_INCLUDE_NETLIST_FILE_NAME = "fabric_netlists.v";
 constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
 constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v";