Merge remote-tracking branch 'origin/master' into replace_yosys

.github/PULL_REQUEST_TEMPLATE/pull_request_template.md

@@ -0,0 +1,33 @@
+---
+name: Pull request
+about: Push a change to this project
+---
+
+### Motivate of the pull request
+- [ ] To address an existing issue. If so, please provide a link to the issue.
+- [ ] Breaking new feature. If so, please decribe details in the description part.
+
+### Describe the technical details
+- What is currently done? (Provide issue link if applicable)
+- What does this pull request change?
+
+### Which part of the code base require a change
+**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
+- [ ] VPR
+- [ ] OpenFPGA libraries
+- [ ] FPGA-Verilog
+- [ ] FPGA-Bitstream
+- [ ] FPGA-SDC
+- [ ] FPGA-SPICE
+- [ ] Flow scripts
+- [ ] Architecture library
+- [ ] Cell library
+
+### Checklist of the pull request
+- [ ] Require code changes. 
+- [ ] Require new tests to be added
+- [ ] Require an update on documentation
+
+### Impact of the pull request
+- [ ] Require a change on Quality of Results (QoR)
+- [ ] Break back-compatibility. If so, please list who may be influenced.

.github/workflows/install_dependency.sh

@@ -26,6 +26,7 @@ sudo apt-get install libxft-dev
 sudo apt-get install libxml++2.6-dev
 sudo apt-get install perl
 sudo apt-get install python
+sudo apt-get install python3-setuptools
 sudo apt-get install python-lxml
 sudo apt-get install tcllib
 sudo apt-get install tcl8.6-dev
@@ -48,3 +49,5 @@ sudo apt-get install g++-9
 sudo apt-get install gcc-9
 sudo apt-get install clang-6.0
 sudo apt-get install clang-8
+# Python dependencies
+python3 -m pip install -r /home/runner/work/OpenFPGA/OpenFPGA/requirements.txt

openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml

@@ -1,10 +1,11 @@
 <!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N8_40nm.xml 
+     This annotation supports the k6_N8_40nm.xml
      - General purpose logic block
        - K = 6, N = 8, I = 32
        - Single mode
      - Routing architecture
        - L = 4, fc_in = 0.15, fc_out = 0.1
+    TEST_VARIABLE = ${TEST_VARIABLE}
   -->
 <openfpga_architecture>
   <technology_library>
@@ -101,7 +102,8 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
     </circuit_model>
     <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
       <design_technology type="cmos"/>
@@ -109,7 +111,8 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
     </circuit_model>
     <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@@ -199,9 +202,9 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
     <!-- End physical pb_type binding in complex block IO -->
 
     <!-- physical pb_type binding in complex block CLB -->

openfpga_flow/scripts/run_fpga_flow.py

@@ -14,9 +14,11 @@ import time
 from datetime import timedelta
 import shlex
 import glob
+import json
 import argparse
 from configparser import ConfigParser, ExtendedInterpolation
 import logging
+from envyaml import EnvYAML
 import glob
 import subprocess
 import threading
@@ -85,11 +87,13 @@ parser.add_argument('--openfpga_shell_template', type=str,
                     help="Sample openfpga shell script")
 parser.add_argument('--openfpga_arch_file', type=str,
                     help="Openfpga architecture file for shell")
+parser.add_argument('--arch_variable_file', type=str, default=None,
+                    help="Openfpga architecture file for shell")
 # parser.add_argument('--openfpga_sim_setting_file', type=str,
 #                     help="Openfpga simulation file for shell")
 # parser.add_argument('--external_fabric_key_file', type=str,
 #                     help="Key file for shell")
-parser.add_argument('--yosys_tmpl', type=str,
+parser.add_argument('--yosys_tmpl', type=str, default=None,
                     help="Alternate yosys template, generates top_module.blif")
 parser.add_argument('--disp', action="store_true",
                     help="Open display while running VPR")
@@ -313,6 +317,15 @@ def read_script_config():
         clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config")
     cad_tools = config["CAD_TOOLS_PATH"]
 
+    if args.arch_variable_file:
+        _, file_extension = os.path.splitext(args.arch_variable_file)
+        if file_extension in [".yml", ".yaml"]:
+            script_env_vars["PATH"].update(
+                EnvYAML(args.arch_variable_file, include_environment=False))
+        if file_extension in [".json", ]:
+            with open(args.arch_variable_file, "r") as fp:
+                script_env_vars["PATH"].update(json.load(fp))
+
 
 def validate_command_line_arguments():
     """
@@ -411,7 +424,7 @@ def prepare_run_directory(run_dir):
     arch_filename = os.path.basename(args.arch_file)
     args.arch_file = os.path.join(run_dir, "arch", arch_filename)
     with open(args.arch_file, 'w', encoding='utf-8') as archfile:
-        archfile.write(tmpl.substitute(script_env_vars["PATH"]))
+        archfile.write(tmpl.safe_substitute(script_env_vars["PATH"]))
 
     if (args.openfpga_arch_file):
         tmpl = Template(
@@ -419,7 +432,7 @@ def prepare_run_directory(run_dir):
         arch_filename = os.path.basename(args.openfpga_arch_file)
         args.openfpga_arch_file = os.path.join(run_dir, "arch", arch_filename)
         with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
-            archfile.write(tmpl.substitute(script_env_vars["PATH"]))
+            archfile.write(tmpl.safe_substitute(script_env_vars["PATH"]))
 
     # Sanitize provided openshell template, if provided
     if (args.openfpga_shell_template):
@@ -474,11 +487,11 @@ def run_yosys_with_abc():
         "LUT_SIZE": lut_size,
         "OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
     }
-    yosys_template = os.path.join(
+    yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
         cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
     with open("yosys.ys", 'w') as archfile:
-        archfile.write(tmpl.substitute(ys_params))
+        archfile.write(tmpl.safe_substitute(ys_params))
     try:
         with open('yosys_output.txt', 'w+') as output:
             process = subprocess.run([cad_tools["yosys_path"], 'yosys.ys'],
@@ -701,7 +714,7 @@ def run_openfpga_shell():
         path_variables[tmpVar] = OpenFPGAArgs[indx+1]
 
     with open(args.top_module+"_run.openfpga", 'w', encoding='utf-8') as archfile:
-        archfile.write(tmpl.substitute(path_variables))
+        archfile.write(tmpl.safe_substitute(path_variables))
     command = [cad_tools["openfpga_shell_path"], "-f",
                args.top_module+"_run.openfpga"]
     run_command("OpenFPGA Shell Run", "openfpgashell.log", command)
@@ -721,7 +734,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
                ]
     if not args.disp:
         command += ["--disp", "off"]
-    else:  
+    else:
         command += ["--disp", "on"]
 
     if route_only:

openfpga_flow/scripts/run_fpga_task.py

@@ -371,6 +371,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
         command += ["--power"]
         command += ["--power_tech", task_gc.get("power_tech_file")]
 
+    if task_gc.get("arch_variable_file"):
+        command += ["--arch_variable_file", task_gc.get("arch_variable_file")]
+
     if task_gc.getboolean("spice_output"):
         command += ["--vpr_fpga_spice"]
 

openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf

@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
+arch_variable_file=${PATH:TASK_DIR}/design_variables.yml 
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga

openfpga_flow/tasks/basic_tests/generate_fabric/design_variables.yml

@@ -0,0 +1 @@
+TEST_VARIABLE: 100

requirements.txt

@@ -0,0 +1,2 @@
+envyaml==1.0.201125
+humanize==3.1.0