diff --git a/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md new file mode 100644 index 000000000..d1c458c04 --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md @@ -0,0 +1,33 @@ +--- +name: Pull request +about: Push a change to this project +--- + +### Motivate of the pull request +- [ ] To address an existing issue. If so, please provide a link to the issue. +- [ ] Breaking new feature. If so, please decribe details in the description part. + +### Describe the technical details +- What is currently done? (Provide issue link if applicable) +- What does this pull request change? + +### Which part of the code base require a change +**In general, modification on existing submodules are not acceptable. You should push changes to upstream.** +- [ ] VPR +- [ ] OpenFPGA libraries +- [ ] FPGA-Verilog +- [ ] FPGA-Bitstream +- [ ] FPGA-SDC +- [ ] FPGA-SPICE +- [ ] Flow scripts +- [ ] Architecture library +- [ ] Cell library + +### Checklist of the pull request +- [ ] Require code changes. +- [ ] Require new tests to be added +- [ ] Require an update on documentation + +### Impact of the pull request +- [ ] Require a change on Quality of Results (QoR) +- [ ] Break back-compatibility. If so, please list who may be influenced. diff --git a/.github/workflows/install_dependency.sh b/.github/workflows/install_dependency.sh index 7f6e323f1..b20184fea 100644 --- a/.github/workflows/install_dependency.sh +++ b/.github/workflows/install_dependency.sh @@ -26,6 +26,7 @@ sudo apt-get install libxft-dev sudo apt-get install libxml++2.6-dev sudo apt-get install perl sudo apt-get install python +sudo apt-get install python3-setuptools sudo apt-get install python-lxml sudo apt-get install tcllib sudo apt-get install tcl8.6-dev @@ -48,3 +49,5 @@ sudo apt-get install g++-9 sudo apt-get install gcc-9 sudo apt-get install clang-6.0 sudo apt-get install clang-8 +# Python dependencies +python3 -m pip install -r /home/runner/work/OpenFPGA/OpenFPGA/requirements.txt diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index c196a8285..5b145ba36 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -1,10 +1,11 @@ @@ -101,7 +102,8 @@ - + + @@ -109,7 +111,8 @@ - + + @@ -199,9 +202,9 @@ - - - + + + diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 94c9dfee6..3501c28c0 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -14,9 +14,11 @@ import time from datetime import timedelta import shlex import glob +import json import argparse from configparser import ConfigParser, ExtendedInterpolation import logging +from envyaml import EnvYAML import glob import subprocess import threading @@ -85,11 +87,13 @@ parser.add_argument('--openfpga_shell_template', type=str, help="Sample openfpga shell script") parser.add_argument('--openfpga_arch_file', type=str, help="Openfpga architecture file for shell") +parser.add_argument('--arch_variable_file', type=str, default=None, + help="Openfpga architecture file for shell") # parser.add_argument('--openfpga_sim_setting_file', type=str, # help="Openfpga simulation file for shell") # parser.add_argument('--external_fabric_key_file', type=str, # help="Key file for shell") -parser.add_argument('--yosys_tmpl', type=str, +parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") parser.add_argument('--disp', action="store_true", help="Open display while running VPR") @@ -313,6 +317,15 @@ def read_script_config(): clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config") cad_tools = config["CAD_TOOLS_PATH"] + if args.arch_variable_file: + _, file_extension = os.path.splitext(args.arch_variable_file) + if file_extension in [".yml", ".yaml"]: + script_env_vars["PATH"].update( + EnvYAML(args.arch_variable_file, include_environment=False)) + if file_extension in [".json", ]: + with open(args.arch_variable_file, "r") as fp: + script_env_vars["PATH"].update(json.load(fp)) + def validate_command_line_arguments(): """ @@ -411,7 +424,7 @@ def prepare_run_directory(run_dir): arch_filename = os.path.basename(args.arch_file) args.arch_file = os.path.join(run_dir, "arch", arch_filename) with open(args.arch_file, 'w', encoding='utf-8') as archfile: - archfile.write(tmpl.substitute(script_env_vars["PATH"])) + archfile.write(tmpl.safe_substitute(script_env_vars["PATH"])) if (args.openfpga_arch_file): tmpl = Template( @@ -419,7 +432,7 @@ def prepare_run_directory(run_dir): arch_filename = os.path.basename(args.openfpga_arch_file) args.openfpga_arch_file = os.path.join(run_dir, "arch", arch_filename) with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile: - archfile.write(tmpl.substitute(script_env_vars["PATH"])) + archfile.write(tmpl.safe_substitute(script_env_vars["PATH"])) # Sanitize provided openshell template, if provided if (args.openfpga_shell_template): @@ -474,11 +487,11 @@ def run_yosys_with_abc(): "LUT_SIZE": lut_size, "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", } - yosys_template = os.path.join( + yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") tmpl = Template(open(yosys_template, encoding='utf-8').read()) with open("yosys.ys", 'w') as archfile: - archfile.write(tmpl.substitute(ys_params)) + archfile.write(tmpl.safe_substitute(ys_params)) try: with open('yosys_output.txt', 'w+') as output: process = subprocess.run([cad_tools["yosys_path"], 'yosys.ys'], @@ -701,7 +714,7 @@ def run_openfpga_shell(): path_variables[tmpVar] = OpenFPGAArgs[indx+1] with open(args.top_module+"_run.openfpga", 'w', encoding='utf-8') as archfile: - archfile.write(tmpl.substitute(path_variables)) + archfile.write(tmpl.safe_substitute(path_variables)) command = [cad_tools["openfpga_shell_path"], "-f", args.top_module+"_run.openfpga"] run_command("OpenFPGA Shell Run", "openfpgashell.log", command) @@ -721,7 +734,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): ] if not args.disp: command += ["--disp", "off"] - else: + else: command += ["--disp", "on"] if route_only: diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 6ab46e1df..7fb0346dc 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -371,6 +371,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): command += ["--power"] command += ["--power_tech", task_gc.get("power_tech_file")] + if task_gc.get("arch_variable_file"): + command += ["--arch_variable_file", task_gc.get("arch_variable_file")] + if task_gc.getboolean("spice_output"): command += ["--vpr_fpga_spice"] diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf index 5d06846c5..db41b7f5a 100644 --- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif +arch_variable_file=${PATH:TASK_DIR}/design_variables.yml [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/design_variables.yml b/openfpga_flow/tasks/basic_tests/generate_fabric/design_variables.yml new file mode 100644 index 000000000..de1dbf341 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/generate_fabric/design_variables.yml @@ -0,0 +1 @@ +TEST_VARIABLE: 100 \ No newline at end of file diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 000000000..7c0776b6f --- /dev/null +++ b/requirements.txt @@ -0,0 +1,2 @@ +envyaml==1.0.201125 +humanize==3.1.0 \ No newline at end of file