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[Flow] disable signal initialization for behavioral verilog generation

This commit is contained in:
tangxifan 2020-11-22 21:13:22 -07:00
parent 5eb04e6fff
commit 617f7e3062
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf
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@ -16,7 +16,7 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml