remove simulation settings from openfpga arch XML
update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis
This commit is contained in:
tangxifan
parent
58807bfcb3
commit
60dd37e086
180
.travis.yml
180
.travis.yml
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@ -14,105 +14,99 @@ cache:
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# Currently sudo is not required, NO ENV is used
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# Currently sudo is not required, NO ENV is used
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# Supported Operating systems
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# Supported Operating systems
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||||||
#os:
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dist: bionic
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||||||
# - linux
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compiler: g++-8
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# - osx
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addons:
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||||||
# Create a matrix to branch the building environment
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apt:
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matrix:
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sources:
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include:
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- ubuntu-toolchain-r-test # For newer GCC
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- os: linux
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- llvm_toolchain-trusty-7
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||||||
# Compiler is specified in ./travis/common.sh
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packages:
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||||||
sudo: false
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- autoconf
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||||||
dist: bionic
|
- automake
|
||||||
compiler: g++-8
|
- bash
|
||||||
addons:
|
- bison
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||||||
apt:
|
- build-essential
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||||||
sources:
|
- cmake
|
||||||
- ubuntu-toolchain-r-test # For newer GCC
|
- ctags
|
||||||
- llvm_toolchain-trusty-7
|
- curl
|
||||||
packages:
|
- doxygen
|
||||||
- autoconf
|
- flex
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||||||
- automake
|
- fontconfig
|
||||||
- bash
|
- g++-8
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||||||
- bison
|
- gcc-8
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||||||
- build-essential
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- gdb
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||||||
- cmake
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- git
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||||||
- ctags
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- gperf
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||||||
- curl
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- iverilog
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||||||
- doxygen
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- libcairo2-dev
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||||||
- flex
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- libevent-dev
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||||||
- fontconfig
|
- libfontconfig1-dev
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||||||
- g++-8
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- liblist-moreutils-perl
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||||||
- gcc-8
|
- libncurses5-dev
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||||||
- gdb
|
- libx11-dev
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||||||
- git
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- libxft-dev
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||||||
- gperf
|
- libxml++2.6-dev
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||||||
- iverilog
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- perl
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||||||
- libcairo2-dev
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- python
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- libevent-dev
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- python-lxml
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||||||
- libfontconfig1-dev
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- texinfo
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||||||
- liblist-moreutils-perl
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- time
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- libncurses5-dev
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- valgrind
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||||||
- libx11-dev
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- zip
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- libxft-dev
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- qt5-default
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- libxml++2.6-dev
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- clang-format-7
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- perl
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#- os: osx
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- python
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# osx_image: xcode10.2 # we target latest MacOS Mojave
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- python-lxml
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# sudo: true
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||||||
- texinfo
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# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
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||||||
- time
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# addons:
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||||||
- valgrind
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# homebrew:
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||||||
- zip
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# packages:
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||||||
- qt5-default
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# - bison
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||||||
- clang-format-7
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# - cmake
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||||||
# - os: osx
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# - ctags
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||||||
# osx_image: xcode10.2 # we target latest MacOS Mojave
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# - flex
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# sudo: true
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# - fontconfig
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# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
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# - git
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# addons:
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# - gcc@6
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||||||
# homebrew:
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# - gcc@4.9
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||||||
# packages:
|
# - gawk
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||||||
# - bison
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# - icarus-verilog
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||||||
# - cmake
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# - libxml++
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||||||
# - ctags
|
# - qt5
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||||||
# - flex
|
|
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# - fontconfig
|
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# - git
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# - gcc@6
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# - gcc@4.9
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# - gawk
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# - icarus-verilog
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# - libxml++
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# - qt5
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before_install:
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before_script:
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||||||
- source .travis/common.sh
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- source .travis/common.sh
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|
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install:
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- DEPS_DIR="${HOME}/deps"
|
|
||||||
- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
|
|
||||||
- |
|
|
||||||
if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
|
|
||||||
CMAKE_URL="https://cmake.org/files/v3.16/cmake-3.16.3-Linux-x86_64.tar.gz"
|
|
||||||
mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
|
|
||||||
export PATH=${DEPS_DIR}/cmake/bin:${PATH}
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echo ${PATH}
|
|
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else
|
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brew install cmake || brew upgrade cmake
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|
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fi
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||||||
- cmake --version
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- cd -
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||||||
- source .travis/install.sh
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- source .travis/install.sh
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||||||
|
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||||||
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stages:
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- name: Test
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if: type != cron
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||||||
|
jobs:
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||||||
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include:
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||||||
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- stage: Test
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name: "OpenFPGA + VPR7 regression tests"
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script:
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- source .travis/build.sh
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- source .travis/openfpga_vpr7_reg_test.sh
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- stage: Test
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name: "OpenFPGA + VPR8 regression tests"
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script:
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- source .travis/build.sh
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- source .travis/openfpga_vpr8_reg_test.sh
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#after_failure:
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# - .travis/after_failure.sh
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||||||
|
#after_success:
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# - .travis/after_success.sh
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script:
|
script:
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- .travis/script.sh
|
- true
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#- .travis/regression.sh
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|
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|
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after_failure:
|
|
||||||
- .travis/after_failure.sh
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|
||||||
|
|
||||||
after_success:
|
|
||||||
- .travis/after_success.sh
|
|
||||||
notifications:
|
notifications:
|
||||||
slack:
|
slack:
|
||||||
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
|
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
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||||||
|
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|
|
@ -0,0 +1,17 @@
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||||||
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#!/bin/bash
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source .travis/common.sh
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set -e
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||||||
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||||||
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start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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mkdir build
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cd build
|
||||||
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||||||
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if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
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cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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||||||
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else
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cmake .. -DCMAKE_BUILD_TYPE=debug
|
||||||
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fi
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||||||
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make -j16
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end_section "OpenFPGA.build"
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@ -4,18 +4,19 @@ source .travis/common.sh
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||||||
set -e
|
set -e
|
||||||
|
|
||||||
## Install necessary package which is not available on Travis CI
|
## Install necessary package which is not available on Travis CI
|
||||||
#export DEPS_DIR="${HOME}/deps"
|
export DEPS_DIR="${HOME}/deps"
|
||||||
#mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
|
mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
|
||||||
## Install CMake
|
# Install CMake
|
||||||
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
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if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
|
||||||
# export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz"
|
export CMAKE_URL="https://cmake.org/files/v3.16/cmake-3.16.3-Linux-x86_64.tar.gz"
|
||||||
# mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
|
mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
|
||||||
# export PATH=${DEPS_DIR}/cmake/bin:${PATH}
|
export PATH=${DEPS_DIR}/cmake/bin:${PATH}
|
||||||
# echo ${PATH}
|
echo ${PATH}
|
||||||
#else
|
else
|
||||||
# brew install cmake || brew upgrade cmake
|
brew install cmake || brew upgrade cmake
|
||||||
#fi
|
fi
|
||||||
# cmake --version
|
cmake --version
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||||||
|
cd -
|
||||||
#
|
#
|
||||||
## Install latest iVerilog. Since no deb is provided, compile from source codes
|
## Install latest iVerilog. Since no deb is provided, compile from source codes
|
||||||
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
|
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
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||||||
|
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|
||||||
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@ -0,0 +1,30 @@
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||||||
|
#!/bin/bash
|
||||||
|
set -e
|
||||||
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||||||
|
start_section "OpenFPGA+VPR7.TaskTun" "${GREEN}..Running_Regression..${NC}"
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||||||
|
cd ${TRAVIS_BUILD_DIR}
|
||||||
|
|
||||||
|
###############################################
|
||||||
|
# OpenFPGA with VPR7
|
||||||
|
# TO BE DEPRECATED
|
||||||
|
##############################################
|
||||||
|
echo -e "Testing single-mode architectures";
|
||||||
|
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
|
||||||
|
#python3 openfpga_flow/scripts/run_fpga_task.py s298
|
||||||
|
|
||||||
|
echo -e "Testing multi-mode architectures";
|
||||||
|
python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
|
||||||
|
|
||||||
|
echo -e "Testing compact routing techniques";
|
||||||
|
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
|
||||||
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|
||||||
|
echo -e "Testing tileable architectures";
|
||||||
|
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
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||||||
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|
||||||
|
echo -e "Testing Verilog generation with explicit port mapping ";
|
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|
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
|
||||||
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|
||||||
|
echo -e "Testing Verilog generation with grid pin duplication ";
|
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python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
|
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|
||||||
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end_section "OpenFPGA+VPR7.TaskTun"
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@ -1,46 +1,9 @@
|
||||||
#!/bin/bash
|
#!/bin/bash
|
||||||
|
|
||||||
source .travis/common.sh
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|
||||||
set -e
|
set -e
|
||||||
|
|
||||||
start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
|
|
||||||
mkdir build
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|
||||||
cd build
|
|
||||||
|
|
||||||
if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
|
|
||||||
cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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|
||||||
else
|
|
||||||
cmake .. -DCMAKE_BUILD_TYPE=debug
|
|
||||||
fi
|
|
||||||
make -j16
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|
||||||
end_section "OpenFPGA.build"
|
|
||||||
|
|
||||||
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|
||||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||||
cd -
|
cd ${TRAVIS_BUILD_DIR}
|
||||||
|
|
||||||
###############################################
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|
||||||
# OpenFPGA with VPR7
|
|
||||||
# TO BE DEPRECATED
|
|
||||||
##############################################
|
|
||||||
echo -e "Testing single-mode architectures";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
|
|
||||||
#python3 openfpga_flow/scripts/run_fpga_task.py s298
|
|
||||||
|
|
||||||
echo -e "Testing multi-mode architectures";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing compact routing techniques";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing tileable architectures";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with explicit port mapping ";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with grid pin duplication ";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
|
|
||||||
|
|
||||||
###############################################
|
###############################################
|
||||||
# OpenFPGA Shell with VPR8
|
# OpenFPGA Shell with VPR8
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||||||
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@ -193,36 +193,3 @@
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||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
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|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
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|
||||||
</slew>
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|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
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|
||||||
</delay>
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|
||||||
</measurement_setting>
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|
||||||
<stimulus>
|
|
||||||
<clock>
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|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
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|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
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|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
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|
||||||
|
|
|
||||||
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|
@ -193,36 +193,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
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</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -193,36 +193,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="500e6" num_cycles="10" slack="0.2"/>
|
|
||||||
<programming frequency="300e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -194,36 +194,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -194,36 +194,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -193,36 +193,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -194,36 +194,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -224,37 +224,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -249,37 +249,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -266,37 +266,3 @@
|
||||||
<!-- END physical pb_type binding in complex block memory -->
|
<!-- END physical pb_type binding in complex block memory -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -278,37 +278,3 @@
|
||||||
<!-- END physical pb_type binding in complex block memory -->
|
<!-- END physical pb_type binding in complex block memory -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -249,37 +249,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -252,37 +252,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -258,37 +258,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -253,37 +253,3 @@
|
||||||
<!-- End physical pb_type binding in complex block CLB -->
|
<!-- End physical pb_type binding in complex block CLB -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -337,37 +337,3 @@
|
||||||
|
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -224,37 +224,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -224,37 +224,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -228,37 +228,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -216,37 +216,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
|
|
@ -215,37 +215,3 @@
|
||||||
<!-- End physical pb_type binding in complex block IO -->
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
</pb_type_annotations>
|
</pb_type_annotations>
|
||||||
</openfpga_architecture>
|
</openfpga_architecture>
|
||||||
<openfpga_simulation_setting>
|
|
||||||
<clock_setting>
|
|
||||||
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
|
|
||||||
<!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
|
|
||||||
<programming frequency="100e6"/>
|
|
||||||
</clock_setting>
|
|
||||||
<simulator_option>
|
|
||||||
<operating_condition temperature="25"/>
|
|
||||||
<output_log verbose="false" captab="false"/>
|
|
||||||
<accuracy type="abs" value="1e-13"/>
|
|
||||||
<runtime fast_simulation="true"/>
|
|
||||||
</simulator_option>
|
|
||||||
<monte_carlo num_simulation_points="2"/>
|
|
||||||
<measurement_setting>
|
|
||||||
<slew>
|
|
||||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
|
||||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
|
||||||
</slew>
|
|
||||||
<delay>
|
|
||||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
|
||||||
</delay>
|
|
||||||
</measurement_setting>
|
|
||||||
<stimulus>
|
|
||||||
<clock>
|
|
||||||
<rise slew_type="abs" slew_time="20e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="20e-12" />
|
|
||||||
</clock>
|
|
||||||
<input>
|
|
||||||
<rise slew_type="abs" slew_time="25e-12" />
|
|
||||||
<fall slew_type="abs" slew_time="25e-12" />
|
|
||||||
</input>
|
|
||||||
</stimulus>
|
|
||||||
</openfpga_simulation_setting>
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue