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[Architecture] Bug fix in architectures that use BRAM

This commit is contained in:
tangxifan 2020-09-24 18:20:55 -06:00
parent d51efd397f
commit 60a14ccbd2
6 changed files with 6 additions and 6 deletions
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2
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
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@ -203,7 +203,7 @@
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="8"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
</circuit_library>
<configuration_protocol>

2
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
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@ -203,7 +203,7 @@
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="8"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
</circuit_library>
<configuration_protocol>

2
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
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@ -203,7 +203,7 @@
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="8"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
<circuit_model type="hard_logic" name="mult_32x32" prefix="mult_32x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_32x32.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_32x32.v">
<design_technology type="cmos"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
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@ -216,7 +216,7 @@
<port type="input" prefix="we2" lib_name="we_b" size="1"/>
<port type="output" prefix="out1" lib_name="q_a" size="32"/>
<port type="output" prefix="out2" lib_name="q_b" size="32"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
<!-- As a fracturable memory, it requires 4 configuration bits to operate in 13 different modes -->
<port type="sram" prefix="mode" size="4" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
</circuit_model>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
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@ -204,7 +204,7 @@
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="32"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
</circuit_library>
<configuration_protocol>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -204,7 +204,7 @@
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="32"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
<circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
<design_technology type="cmos"/>