From 60a14ccbd21184ce04ce170497f0591572db42fa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 24 Sep 2020 18:20:55 -0600
Subject: [PATCH] [Architecture] Bug fix in architectures that use BRAM

---
 .../k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml        | 2 +-
 .../k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml   | 2 +-
 ...frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 2 +-
 ...rac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 2 +-
 .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml            | 2 +-
 .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml        | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
index 20a91779d..09fe2c681 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
@@ -203,7 +203,7 @@
       <port type="input" prefix="wen" size="1"/>
       <port type="input" prefix="ren" size="1"/>
       <port type="output" prefix="d_out" size="8"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
index 89eb8d37f..79980dacc 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
@@ -203,7 +203,7 @@
       <port type="input" prefix="wen" size="1"/>
       <port type="input" prefix="ren" size="1"/>
       <port type="output" prefix="d_out" size="8"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
index 6dffbfd2c..d5c6fff86 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
@@ -203,7 +203,7 @@
       <port type="input" prefix="wen" size="1"/>
       <port type="input" prefix="ren" size="1"/>
       <port type="output" prefix="d_out" size="8"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
     <circuit_model type="hard_logic" name="mult_32x32" prefix="mult_32x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_32x32.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_32x32.v">
       <design_technology type="cmos"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index 937dd27f1..3b1ab1732 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -216,7 +216,7 @@
       <port type="input" prefix="we2" lib_name="we_b" size="1"/>
       <port type="output" prefix="out1" lib_name="q_a" size="32"/>
       <port type="output" prefix="out2" lib_name="q_b" size="32"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
       <!-- As a fracturable memory, it requires 4 configuration bits to operate in 13 different modes -->
       <port type="sram" prefix="mode" size="4" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 12117aad3..92f56df47 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -204,7 +204,7 @@
       <port type="input" prefix="wen" size="1"/>
       <port type="input" prefix="ren" size="1"/>
       <port type="output" prefix="d_out" size="32"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index f3a821c95..2543f9096 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -204,7 +204,7 @@
       <port type="input" prefix="wen" size="1"/>
       <port type="input" prefix="ren" size="1"/>
       <port type="output" prefix="d_out" size="32"/>
-      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
     <circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
       <design_technology type="cmos"/>