adapt LUT Verilog writer

openfpga/src/fpga_verilog/verilog_lut.cpp

@@ -0,0 +1,78 @@
+/********************************************************************
+ * This file includes functions to generate Verilog submodules for LUTs
+ ********************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_lut.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Print Verilog modules for the Look-Up Tables (LUTs) 
+ * in the circuit library
+ ********************************************************************/
+void print_verilog_submodule_luts(ModuleManager& module_manager,
+                                  std::vector<std::string>& netlist_names,
+                                  const CircuitLibrary& circuit_lib,
+                                  const std::string& verilog_dir,
+                                  const std::string& submodule_dir,
+                                  const bool& use_explicit_port_map) {
+  std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME);
+
+  std::fstream fp;
+
+  /* Create the file stream */
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(verilog_fname.c_str(), fp); 
+
+  /* Create file */
+  VTR_LOG("Writing Verilog netlist for LUTs '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Look-Up Tables"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Search for each LUT circuit model */
+  for (const auto& lut_model : circuit_lib.models()) {
+    /* Bypass user-defined and non-LUT modules */
+    if ( (!circuit_lib.model_verilog_netlist(lut_model).empty()) 
+      || (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
+      continue;
+    }
+    /* Find the module id */
+    ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model));
+    VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
+    write_verilog_module_to_file(fp, module_manager, lut_module, 
+                                 use_explicit_port_map || circuit_lib.dump_explicit_port_map(lut_model));
+  }
+
+  /* Close the file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_lut.h

@@ -0,0 +1,29 @@
+#ifndef VERILOG_LUT_H
+#define VERILOG_LUT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_luts(ModuleManager& module_manager,
+                                  std::vector<std::string>& netlist_names,
+                                  const CircuitLibrary& circuit_lib,
+                                  const std::string& verilog_dir,
+                                  const std::string& submodule_dir,
+                                  const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif