riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Travis failure debug

This commit is contained in:
Ganesh Gore 2019-11-01 23:06:33 -06:00
parent a880802803
commit 5c8ca81645
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
.travis/script.sh
View File

@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug
#python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
# echo -e "Testing multi-mode architectures";
# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
# echo -e "Testing compact routing techniques";
# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
# echo -e "Testing tileable architectures";
# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
# echo -e "Testing Verilog generation with explicit port mapping ";
# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
end_section "OpenFPGA.TaskTun"