From 5c8ca81645c2db583ffa6a7f61e51dff1f4d1f2a Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 23:06:33 -0600 Subject: [PATCH] Travis failure debug --- .travis/script.sh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index bbd72cec4..804d7303e 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,19 +19,19 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode -#python3 openfpga_flow/scripts/run_fpga_task.py s298 +python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug +#python3 openfpga_flow/scripts/run_fpga_task.py s298 -echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 +# echo -e "Testing multi-mode architectures"; +# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 -echo -e "Testing compact routing techniques"; -python3 openfpga_flow/scripts/run_fpga_task.py compact_routing +# echo -e "Testing compact routing techniques"; +# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing -echo -e "Testing tileable architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +# echo -e "Testing tileable architectures"; +# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing -echo -e "Testing Verilog generation with explicit port mapping "; -python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog +# echo -e "Testing Verilog generation with explicit port mapping "; +# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog end_section "OpenFPGA.TaskTun"