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Simple argument shuffle

This commit is contained in:
Ganesh Gore 2019-11-01 18:21:26 -06:00
parent 27005d6640
commit 595d2d3070
2 changed files with 3 additions and 2 deletions
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3
openfpga_flow/scripts/run_fpga_flow.py
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@ -711,7 +711,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
command += ["--fpga_verilog_print_input_blif_testbench"] command += ["--fpga_verilog_print_input_blif_testbench"]
if args.vpr_fpga_verilog_print_autocheck_top_testbench: if args.vpr_fpga_verilog_print_autocheck_top_testbench:
command += ["--fpga_verilog_print_autocheck_top_testbench", command += ["--fpga_verilog_print_autocheck_top_testbench",
args.top_module+"_output_verilog.v"] # args.vpr_fpga_verilog_print_autocheck_top_testbench]
os.path.join(args.run_dir, args.top_module+"_output_verilog.v")]
if args.vpr_fpga_verilog_include_timing: if args.vpr_fpga_verilog_include_timing:
command += ["--fpga_verilog_include_timing"] command += ["--fpga_verilog_include_timing"]
if args.vpr_fpga_verilog_explicit_mapping: if args.vpr_fpga_verilog_explicit_mapping:

2
openfpga_flow/scripts/run_fpga_task.py
View File

@ -367,7 +367,7 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
if task_gc.getboolean("verilog_output"): if task_gc.getboolean("verilog_output"):
command += ["--vpr_fpga_verilog"] command += ["--vpr_fpga_verilog"]
command += ["--vpr_fpga_verilog_dir", "."] command += ["--vpr_fpga_verilog_dir", curr_job_dir]
command += ["--vpr_fpga_x2p_rename_illegal_port"] command += ["--vpr_fpga_x2p_rename_illegal_port"]
# Add other paramters to pass # Add other paramters to pass