diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 110a0f506..83850ffe4 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -711,7 +711,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
             command += ["--fpga_verilog_print_input_blif_testbench"]
         if args.vpr_fpga_verilog_print_autocheck_top_testbench:
             command += ["--fpga_verilog_print_autocheck_top_testbench",
-                        args.top_module+"_output_verilog.v"]
+                        # args.vpr_fpga_verilog_print_autocheck_top_testbench]
+                        os.path.join(args.run_dir, args.top_module+"_output_verilog.v")]
         if args.vpr_fpga_verilog_include_timing:
             command += ["--fpga_verilog_include_timing"]
         if args.vpr_fpga_verilog_explicit_mapping:
diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py
index a46c99e79..061ef1248 100644
--- a/openfpga_flow/scripts/run_fpga_task.py
+++ b/openfpga_flow/scripts/run_fpga_task.py
@@ -367,7 +367,7 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
 
     if task_gc.getboolean("verilog_output"):
         command += ["--vpr_fpga_verilog"]
-        command += ["--vpr_fpga_verilog_dir", "."]
+        command += ["--vpr_fpga_verilog_dir", curr_job_dir]
         command += ["--vpr_fpga_x2p_rename_illegal_port"]
 
     # Add other paramters to pass