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[Test] Update regression test script

This commit is contained in:
tangxifan 2021-10-06 12:10:37 -07:00
parent b98a8ec718
commit 554018449e
1 changed files with 2 additions and 1 deletions
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openfpga_flow/regression_test_scripts/basic_reg_test.sh
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@ -83,7 +83,8 @@ echo -e "Testing separated Verilog fabric netlists and testbench locations";
run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
run-task basic_tests/fixed_simulation_settings --debug --show_thread_logs run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq --debug --show_thread_logs
run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq --debug --show_thread_logs
echo -e "Testing Secured FPGA fabrics"; echo -e "Testing Secured FPGA fabrics";
run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs