From 554018449eae53fb8cefd37c0bd4f1006cab0035 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Oct 2021 12:10:37 -0700 Subject: [PATCH] [Test] Update regression test script --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c593994d8..5381920fe 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -83,7 +83,8 @@ echo -e "Testing separated Verilog fabric netlists and testbench locations"; run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -run-task basic_tests/fixed_simulation_settings --debug --show_thread_logs +run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq --debug --show_thread_logs +run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq --debug --show_thread_logs echo -e "Testing Secured FPGA fabrics"; run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs