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[Test] Bug fix in the test case using lut adder

This commit is contained in:
tangxifan 2021-02-23 16:59:46 -07:00
parent db71cc8a16
commit 53df7f69e7
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
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@ -32,7 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
##########################
# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR
bench1_top = adder_8
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=