From 53df7f69e743663e4cb93cdb8fdb34679f37598c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 16:59:46 -0700 Subject: [PATCH] [Test] Bug fix in the test case using lut adder --- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 1d3f0ff86..b736cd5e9 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -32,7 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad ########################## # Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR bench1_top = adder_8 -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=