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move mux_lib to fpga_x2p_setup

This commit is contained in:
tangxifan 2019-10-19 19:13:52 -06:00
parent 04f0fbebf7
commit 520e145af2
5 changed files with 8 additions and 6 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c
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@ -60,7 +60,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
/* Xifan TANG: Synthesizable verilog dumping */ /* Xifan TANG: Synthesizable verilog dumping */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) {
vpr_fpga_verilog(module_manager, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); vpr_fpga_verilog(module_manager, mux_lib, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);
} }
/* Xifan Tang: Bitstream Generator */ /* Xifan Tang: Bitstream Generator */

3
vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c
View File

@ -51,7 +51,8 @@ void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) {
return; return;
} }
vpr_fpga_verilog(env->module_manager, env->vpr_setup, env->arch, vpr_fpga_verilog(env->module_manager, env->mux_lib,
env->vpr_setup, env->arch,
env->vpr_setup.FileNameOpts.CircuitName); env->vpr_setup.FileNameOpts.CircuitName);
return; return;

3
vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h
View File

@ -2,9 +2,9 @@
#define SHELL_TYPES_H #define SHELL_TYPES_H
#include "vpr_types.h" #include "vpr_types.h"
#include "mux_library.h"
#include "module_manager.h" #include "module_manager.h"
typedef struct s_cmd_category t_cmd_category; typedef struct s_cmd_category t_cmd_category;
typedef struct s_shell_cmd t_shell_cmd; typedef struct s_shell_cmd t_shell_cmd;
typedef struct s_shell_env t_shell_env; typedef struct s_shell_env t_shell_env;
@ -35,6 +35,7 @@ struct s_shell_cmd {
struct s_shell_env { struct s_shell_env {
ModuleManager module_manager; ModuleManager module_manager;
MuxLibrary mux_lib;
t_arch arch; t_arch arch;
t_vpr_setup vpr_setup; t_vpr_setup vpr_setup;
t_shell_cmd* cmd; t_shell_cmd* cmd;

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -118,6 +118,7 @@ void free_global_routing_conf_bits() {
/* Top-level function*/ /* Top-level function*/
void vpr_fpga_verilog(ModuleManager& module_manager, void vpr_fpga_verilog(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
t_vpr_setup vpr_setup, t_vpr_setup vpr_setup,
t_arch Arch, t_arch Arch,
char* circuit_name) { char* circuit_name) {
@ -159,9 +160,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
t_sram_orgz_info* sram_verilog_orgz_info = NULL; t_sram_orgz_info* sram_verilog_orgz_info = NULL;
/* Build Multiplexer library */
MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch);
/* 0. basic units: inverter, buffers and pass-gate logics, */ /* 0. basic units: inverter, buffers and pass-gate logics, */
/* Check if the routing architecture we support*/ /* Check if the routing architecture we support*/
if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h
View File

@ -2,9 +2,11 @@
#define VERILOG_API_H #define VERILOG_API_H
#include "vpr_types.h" #include "vpr_types.h"
#include "mux_library.h"
#include "module_manager.h" #include "module_manager.h"
void vpr_fpga_verilog(ModuleManager& module_manager, void vpr_fpga_verilog(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
t_vpr_setup vpr_setup, t_vpr_setup vpr_setup,
t_arch Arch, t_arch Arch,
char* circuit_name); char* circuit_name);