continuing simple documentation
This commit is contained in:
Steve Corey
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"metadata": {},
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"metadata": {},
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"source": [
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"source": [
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"# The Architecture format\n",
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"# The Architecture format\n",
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"A complete FPGA is specified in an architecture XML file and is wrapped in an `<architecture>` tag. `v8_example_arch.xml` defines a simple FPGA.\n",
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"A complete FPGA is specified in an architecture XML file. The FPGA specification is wrapped in an `<architecture>` tag; `v8_example_arch.xml` defines a simple FPGA.\n",
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"\n",
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"\n",
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"### [`<models>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#recognized-blif-models-models)\n",
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"### [`<models>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#recognized-blif-models-models)\n",
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"The first element in the architecture is `<models>`, which describes `blif` circuit models that the FPGA uses. The models `.names`, `.latch`, `.input`, and `.output` are automatically recognized and don't need to be specified in this section. The `v8_example_arch.xml` architecture is simple enough to not need any additional models specified here.\n",
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"The first element in the architecture is `<models>`, which describes `blif` circuit models that the FPGA uses. The models `.names`, `.latch`, `.input`, and `.output` are automatically recognized and don't need to be specified in this section. The `v8_example_arch.xml` architecture is simple enough to not need any additional models specified here.\n",
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"metadata": {},
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"metadata": {},
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"source": [
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"source": [
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"## [`<complexblocklist>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#complex-blocks)\n",
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"## [`<complexblocklist>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#complex-blocks)\n",
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"In this example architecture, two complex blocks are defined: An input/output block, and a configurable logic block (CLB).\n",
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"\n",
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"\n",
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"### Input and Output block\n",
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"`<pb_type name=\"io\" capacity=\"3\">` begins the definition of the I/O block. `pb_type` is the tag that indicates a primitive block is being defined, and multiple `pb_type`'s can be nested. `capacity` is only allowed in an I/O block, and indicates how many inputs or outpus the block will have.\n",
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"\n",
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"`<input name=\"outpad\" num_pins=\"1\"/>` defines what might be considered an *output* from the FPGA, which is why it is given the name `outpad`: signals coming out of the FPGA are routed to the *input* of this block and then sent out of the *outpad* to the outside world. Similarly, a signal from the outside world comes in the *inpad* and then sent out the *output* of the block to then be routed through the FPGA. Thus the *input* to the FPGA is defined by `<output name=\"inpad\" num_pins=\"1\"/>`. \n",
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"\n",
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"An I/O block can only be an input or an output, and the mode defines the behavior. `<mode name=\"inpad\">` begins the input behavior. `<pb_type name=\"inpad\" blif_model=\".input\" num_pb=\"1\">` gives the physical block a name `inpad`, associates it with the `.input` of the blif model, and indicates there is 1 of these `inpad`s in the parent pb_type of `io`.\n",
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"\n",
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"`<output name=\"inpad\" num_pins=\"1\"/>` says that there is one output of the block named `inpad`. The signal comes in the *inpad* and is sent *out* of this block to the rest of the FPGA.\n",
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"\n",
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"The `<interconnect>` section makes connections between the block's pins. `<direct name=\"inpad\" input=\"inpad.inpad\" output=\"io.inpad\">` creates a direct connection named `inpad`, connects its input to `inpad.inpad` which is the output of the `inpad` block, and connects its ouput to `io.inpad` which is the ouput of the `io` block.\n",
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"\n",
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"The `<delay_constant>` tag specifies the delay between the in_port and the out_port of the primitive block.\n",
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"\n",
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"`<mode name=\"outpad\">` defines the other mode of this block, and is analagous to the `inpad` definition.\n",
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"\n",
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"\n",
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"# Skip I/O for now...\n",
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"\n",
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"\n",
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"\n",
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"\n",
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"## Logic Blocks\n",
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"## Logic Blocks\n",
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"\n",
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"\n",
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"Line 115 is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n",
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"`<pb_type name=\"clb\">` is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a primitive block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 3 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n",
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"\n",
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"\n",
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"Line 121 defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"fle\" num_pb=\"4\">` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n",
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"`<pb_type name=\"ble4\" num_pb=\"3\">` defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"ble4\" num_pb=\"3\">` attribute indicates that 3 of these BLEs called `ble4` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n",
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"\n",
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"\n",
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"Skipping down to line 134, the core lookup-table of the BLE is defined: `<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">`. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n",
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"`<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">` defines the lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n",
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"\n",
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"\n",
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"Line 147 defines the flip-flop in the BLE: `<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">`: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n",
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"`<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">` defines the flip-flop in the BLE: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n",
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"\n",
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"\n",
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"Skipping back up to line 126, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 128 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n",
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"The `<interconnect>` section wires the blocks together. The input of `ble4` is connected to the input of `lut4`, the output of `lut4` is connected to the D-input of `ff`. The clk inputs are wired together. Finally, a mux is defined to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`.\n",
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"\n",
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"\n",
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"Moving back down to line 155, `<interconnect>` indicates how the blocks are connected. The `<direct>` element means to simply wire the nets together. Line 156 wires the input of `ble4` to the input of `lut4`, line 157 wires the output of `lut4` to the D-input of `ff`. Line 161 wires the clk inputs together. Line 162 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`."
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"That completes the *ble* definition, now the *clb* needs to be completed with its `<interconnect>` section. The `<complete>` tag indicates a fully connected crossbar, so any input of the clb can be routed to any of the bles. Also, `input=\"clb.I ble4[2:0].out\"` means that there are two inputs to the crossbar: the input to the clb as well as the output of the bles, giving a feedback configuration. The output of the crossbar is connected to the inputs of the bles. Finally, the output of the bles are connected to the output of the clb.\n",
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"\n",
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"At the end of the top-level `pb_type` definition, the configuration of pins is specified. `<fc in_type=\"frac\" in_val=\"0.15\" out_type=\"frac\" out_val=\"0.25\"/>` shows the percentage of tracks in the channel drive the block's pins. \n",
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"\n",
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"`<pinlocations pattern=\"spread\"/>` says that the pins should be spread evenly around the edges of the block."
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]
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]
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},
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{
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"cell_type": "markdown",
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"source": [
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"# Multimode CLB\n",
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"In the I/O section of the architecture, the `<mode>` tag was used to define different modes for the block. One mode was for input, the other mode for output. Modes are also used in CLBs. Open the file `OpenFPGA/tutorial/02_multimode_arch.xml`. It defines two modes for its CLB: a 6-LUT, or two 5-LUTs with shared inputs.\n",
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"\n",
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"Find the line `<pb_type name=\"clb\" area=\"53894\">` which begins the definition of the CLB. The next few lines define the inputs and outputs: 40 input pins, 20 output pins, and a clock pin. The inputs are marked with `equivalent=\"full\"` which indicates that the inputs have logical equivalence so their locations may be freely swapped. The outputs are `equivalent=\"none\"` so they may not be swapped.\n",
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"\n",
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"The next primitive block is `<pb_type name=\"fle\" num_pb=\"10\">` which is a fracturable logic element that contains the two different modes of this CLB. There are 10 of this `fle` in the CLB. Each `fle` has 6 inputs, 2 outputs, and one clock pin.\n",
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"\n",
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"### First Mode\n",
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"`<mode name=\"n2_lut5\">` begins the definition of the first mode. Moving down the architecture file, we see that in this mode, the `fle` contains one `lut5inter` block which contains two `ble5` blocks. The `ble5` blocks have 5 inputs and 1 output. The next group of lines define the LUT and FF in `ble5`.\n",
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"\n",
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"Moving down to the second `<interconnect>` block:\n",
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"```\n",
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"<interconnect>\n",
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" <direct name=\"direct1\" input=\"lut5inter.in\" output=\"ble5[0:0].in\"/>\n",
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" <direct name=\"direct2\" input=\"lut5inter.in\" output=\"ble5[1:1].in\"/>\n",
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" <direct name=\"direct3\" input=\"ble5[1:0].out\" output=\"lut5inter.out\"/> \n",
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" <complete name=\"complete1\" input=\"lut5inter.clk\" output=\"ble5[1:0].clk\"/> \n",
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"</interconnect>\n",
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"```\n",
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"we see that the input of `lut5inter` is connected to the inputs of both the first and second `ble5` blocks. Then the two outputs of the two `ble5` blocks go to the two outputs of `lut5inter`. Finally, there is a fully connected crossbar that connects the `lut5inter` clock input to the two `ble5` clock inputs.\n",
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"\n",
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"Finishing out this mode, there is the last interconnect section. Note the line: `<direct name=\"direct1\" input=\"fle.in[4:0]\" output=\"lut5inter.in\"/>`. It shows that out of the 6 `fle` input lines, only the first 5 lines are connected to `lut5inter`. The remaining line is unused.\n",
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"\n",
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"### Second Mode\n"
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]
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<!--
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Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
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Simple architecture file for vpr version 8 consisting of clusters of BLEs, each BLE contains a 4-LUT+FF pair. Delay models from 90nm PTM.
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: This simple architecture needs no models defined here. Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch) that describe them.
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-->
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<models>
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</models>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout>
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<auto_layout aspect_ratio="1.000000">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
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<area grid_logic_tile_area="7238.080078"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="switchblock" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="7.958000e-11" mux_trans_size="2.074780" buf_size="19.261999"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.362000e-11" mux_trans_size="1.240240" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
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<mux name="switchblock"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<!-- Define I/O pads begin -->
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
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<pb_type name="io" capacity="3">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs.
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Delays below come from Ian Kuon. They are small, so they should be interpreted as
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the delays to and from registers in the I/O (and generally I/Os are registered
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today and that is when you timing analyze them.
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-->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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<pb_type name="clb" area="53894">
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe fracturable logic element.
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Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
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The outputs of the fracturable logic element can be optionally registered
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-->
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
|
||||||
|
<!-- Dual 5-LUT mode definition begin -->
|
||||||
|
<mode name="n2_lut5">
|
||||||
|
<pb_type name="lut5inter" num_pb="1">
|
||||||
|
<input name="in" num_pins="5"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="ble5" num_pb="2">
|
||||||
|
<input name="in" num_pins="5"/>
|
||||||
|
<output name="out" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
|
||||||
|
<!-- Define the LUT -->
|
||||||
|
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||||
|
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
|
we instead take the average of these numbers to get more stable results
|
||||||
|
82e-12
|
||||||
|
173e-12
|
||||||
|
261e-12
|
||||||
|
263e-12
|
||||||
|
398e-12
|
||||||
|
-->
|
||||||
|
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</pb_type>
|
||||||
|
|
||||||
|
<!-- Define the flip-flop -->
|
||||||
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||||
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
|
</pb_type>
|
||||||
|
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
|
||||||
|
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
|
||||||
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||||
|
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
|
||||||
|
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]" />
|
||||||
|
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]" />
|
||||||
|
</mux>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
||||||
|
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
||||||
|
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
||||||
|
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
||||||
|
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- Dual 5-LUT mode definition end -->
|
||||||
|
<!-- 6-LUT mode definition begin -->
|
||||||
|
<mode name="n1_lut6">
|
||||||
|
<!-- Define 6-LUT mode -->
|
||||||
|
<pb_type name="ble6" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
|
||||||
|
<!-- Define LUT -->
|
||||||
|
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||||
|
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
|
we instead take the average of these numbers to get more stable results
|
||||||
|
82e-12
|
||||||
|
173e-12
|
||||||
|
261e-12
|
||||||
|
263e-12
|
||||||
|
398e-12
|
||||||
|
397e-12
|
||||||
|
-->
|
||||||
|
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</pb_type>
|
||||||
|
|
||||||
|
<!-- Define flip-flop -->
|
||||||
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||||
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
|
</pb_type>
|
||||||
|
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||||
|
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||||
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||||
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||||
|
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
|
||||||
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
|
||||||
|
</mux>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||||||
|
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- 6-LUT mode definition end -->
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||||
|
The delays below come from Stratix IV. the delay through a connection block
|
||||||
|
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||||
|
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||||
|
delay within the crossbar is 95 ps.
|
||||||
|
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||||
|
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||||
|
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||||
|
to get the part that should be marked on the crossbar. -->
|
||||||
|
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||||||
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in" />
|
||||||
|
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
|
||||||
|
</complete>
|
||||||
|
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||||
|
</complete>
|
||||||
|
|
||||||
|
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||||
|
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||||
|
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||||
|
naive specification).
|
||||||
|
-->
|
||||||
|
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||||||
|
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||||||
|
</interconnect>
|
||||||
|
|
||||||
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||||
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||||
|
|
||||||
|
<pinlocations pattern="spread"/>
|
||||||
|
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define general purpose logic block (CLB) ends -->
|
||||||
|
|
||||||
|
</complexblocklist>
|
||||||
|
</architecture>
|
||||||
Loading…
Reference in New Issue