diff --git a/tutorial/01_architecture.ipynb b/tutorial/01_architecture.ipynb index 9ce2b584a..53f17d302 100644 --- a/tutorial/01_architecture.ipynb +++ b/tutorial/01_architecture.ipynb @@ -1,11 +1,11 @@ { "cells": [ -{ + { "cell_type": "markdown", "metadata": {}, "source": [ "# The Architecture format\n", - "A complete FPGA is specified in an architecture XML file and is wrapped in an `` tag. `v8_example_arch.xml` defines a simple FPGA.\n", + "A complete FPGA is specified in an architecture XML file. The FPGA specification is wrapped in an `` tag; `v8_example_arch.xml` defines a simple FPGA.\n", "\n", "### [``](http://docs.verilogtorouting.org/en/latest/arch/reference/#recognized-blif-models-models)\n", "The first element in the architecture is ``, which describes `blif` circuit models that the FPGA uses. The models `.names`, `.latch`, `.input`, and `.output` are automatically recognized and don't need to be specified in this section. The `v8_example_arch.xml` architecture is simple enough to not need any additional models specified here.\n", @@ -42,27 +42,52 @@ "metadata": {}, "source": [ "## [``](http://docs.verilogtorouting.org/en/latest/arch/reference/#complex-blocks)\n", + "In this example architecture, two complex blocks are defined: An input/output block, and a configurable logic block (CLB).\n", "\n", + "### Input and Output block\n", + "`` begins the definition of the I/O block. `pb_type` is the tag that indicates a primitive block is being defined, and multiple `pb_type`'s can be nested. `capacity` is only allowed in an I/O block, and indicates how many inputs or outpus the block will have.\n", + "\n", + "`` defines what might be considered an *output* from the FPGA, which is why it is given the name `outpad`: signals coming out of the FPGA are routed to the *input* of this block and then sent out of the *outpad* to the outside world. Similarly, a signal from the outside world comes in the *inpad* and then sent out the *output* of the block to then be routed through the FPGA. Thus the *input* to the FPGA is defined by ``. \n", + "\n", + "An I/O block can only be an input or an output, and the mode defines the behavior. `` begins the input behavior. `` gives the physical block a name `inpad`, associates it with the `.input` of the blif model, and indicates there is 1 of these `inpad`s in the parent pb_type of `io`.\n", + "\n", + "`` says that there is one output of the block named `inpad`. The signal comes in the *inpad* and is sent *out* of this block to the rest of the FPGA.\n", + "\n", + "The `` section makes connections between the block's pins. `` creates a direct connection named `inpad`, connects its input to `inpad.inpad` which is the output of the `inpad` block, and connects its ouput to `io.inpad` which is the ouput of the `io` block.\n", + "\n", + "The `` tag specifies the delay between the in_port and the out_port of the primitive block.\n", + "\n", + "`` defines the other mode of this block, and is analagous to the `inpad` definition.\n", "\n", - "# Skip I/O for now...\n", "\n", "\n", "## Logic Blocks\n", "\n", - "Line 115 is where the general purpuse *complex logic block* or *clb* definition begins. `` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n", + "`` is where the general purpuse *complex logic block* or *clb* definition begins. `` is the tag to define a primitive block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 3 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n", "\n", - "Line 121 defines the *basic logic element* or *BLE* that makes up the clb. The `` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n", + "`` defines the *basic logic element* or *BLE* that makes up the clb. The `` attribute indicates that 3 of these BLEs called `ble4` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n", "\n", - "Skipping down to line 134, the core lookup-table of the BLE is defined: ``. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `` attribute specifies the propogation delay through the LUT's inputs to output.\n", + "`` defines the lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `` attribute specifies the propogation delay through the LUT's inputs to output.\n", "\n", - "Line 147 defines the flip-flop in the BLE: ``: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n", + "`` defines the flip-flop in the BLE: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n", "\n", - "Skipping back up to line 126, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 128 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n", + "The `` section wires the blocks together. The input of `ble4` is connected to the input of `lut4`, the output of `lut4` is connected to the D-input of `ff`. The clk inputs are wired together. Finally, a mux is defined to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`.\n", "\n", - "Moving back down to line 155, `` indicates how the blocks are connected. The `` element means to simply wire the nets together. Line 156 wires the input of `ble4` to the input of `lut4`, line 157 wires the output of `lut4` to the D-input of `ff`. Line 161 wires the clk inputs together. Line 162 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`." + "That completes the *ble* definition, now the *clb* needs to be completed with its `` section. The `` tag indicates a fully connected crossbar, so any input of the clb can be routed to any of the bles. Also, `input=\"clb.I ble4[2:0].out\"` means that there are two inputs to the crossbar: the input to the clb as well as the output of the bles, giving a feedback configuration. The output of the crossbar is connected to the inputs of the bles. Finally, the output of the bles are connected to the output of the clb.\n", + "\n", + "At the end of the top-level `pb_type` definition, the configuration of pins is specified. `` shows the percentage of tracks in the channel drive the block's pins. \n", + "\n", + "`` says that the pins should be spread evenly around the edges of the block." ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [] } - ], + ], "metadata": { "kernelspec": { "display_name": "Python 3", diff --git a/tutorial/02_multimode.ipynb b/tutorial/02_multimode.ipynb new file mode 100644 index 000000000..26932f8a3 --- /dev/null +++ b/tutorial/02_multimode.ipynb @@ -0,0 +1,62 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Multimode CLB\n", + "In the I/O section of the architecture, the `` tag was used to define different modes for the block. One mode was for input, the other mode for output. Modes are also used in CLBs. Open the file `OpenFPGA/tutorial/02_multimode_arch.xml`. It defines two modes for its CLB: a 6-LUT, or two 5-LUTs with shared inputs.\n", + "\n", + "Find the line `` which begins the definition of the CLB. The next few lines define the inputs and outputs: 40 input pins, 20 output pins, and a clock pin. The inputs are marked with `equivalent=\"full\"` which indicates that the inputs have logical equivalence so their locations may be freely swapped. The outputs are `equivalent=\"none\"` so they may not be swapped.\n", + "\n", + "The next primitive block is `` which is a fracturable logic element that contains the two different modes of this CLB. There are 10 of this `fle` in the CLB. Each `fle` has 6 inputs, 2 outputs, and one clock pin.\n", + "\n", + "### First Mode\n", + "`` begins the definition of the first mode. Moving down the architecture file, we see that in this mode, the `fle` contains one `lut5inter` block which contains two `ble5` blocks. The `ble5` blocks have 5 inputs and 1 output. The next group of lines define the LUT and FF in `ble5`.\n", + "\n", + "Moving down to the second `` block:\n", + "```\n", + "\n", + " \n", + " \n", + " \n", + " \n", + "\n", + "```\n", + "we see that the input of `lut5inter` is connected to the inputs of both the first and second `ble5` blocks. Then the two outputs of the two `ble5` blocks go to the two outputs of `lut5inter`. Finally, there is a fully connected crossbar that connects the `lut5inter` clock input to the two `ble5` clock inputs.\n", + "\n", + "Finishing out this mode, there is the last interconnect section. Note the line: ``. It shows that out of the 6 `fle` input lines, only the first 5 lines are connected to `lut5inter`. The remaining line is unused.\n", + "\n", + "### Second Mode\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.6.5" + } + }, + "nbformat": 4, + "nbformat_minor": 2 +} diff --git a/tutorial/02_multimode_arch.xml b/tutorial/02_multimode_arch.xml new file mode 100644 index 000000000..99822182b --- /dev/null +++ b/tutorial/02_multimode_arch.xml @@ -0,0 +1,290 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +