Added architecture and replaced variables
This commit is contained in:
Ganesh Gore
parent
cb5b16c949
commit
5116aa2ae1
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@ -194,7 +194,7 @@
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</input>
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</input>
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</stimulate>
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</stimulate>
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</parameters>
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</parameters>
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<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
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<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
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<transistors pn_ratio="2" model_ref="M">
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<transistors pn_ratio="2" model_ref="M">
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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@ -344,7 +344,7 @@
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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</circuit_model>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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@ -386,7 +386,7 @@
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
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<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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@ -398,7 +398,7 @@
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<port type="output" prefix="Qb" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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@ -411,7 +411,7 @@
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<port type="output" prefix="inpad" size="1"/>
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<port type="output" prefix="inpad" size="1"/>
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</circuit_model>
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</circuit_model>
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<!-- Hard logic definition for heterogenous blocks -->
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<!-- Hard logic definition for heterogenous blocks -->
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<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
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<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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@ -421,7 +421,7 @@
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<port type="output" prefix="sumout" size="1"/>
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<port type="output" prefix="sumout" size="1"/>
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<port type="output" prefix="cout" size="1"/>
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<port type="output" prefix="cout" size="1"/>
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</circuit_model>
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</circuit_model>
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<circuit_model type="hard_logic" name="dpram" prefix="dpram" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/spram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/memory_wrapper.v">
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<circuit_model type="hard_logic" name="dpram" prefix="dpram" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/spram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/memory_wrapper.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="buf1"/>
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<input_buffer exist="on" circuit_model_name="buf1"/>
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<output_buffer exist="on" circuit_model_name="buf1"/>
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<output_buffer exist="on" circuit_model_name="buf1"/>
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@ -433,7 +433,7 @@
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<port type="output" prefix="d_out" size="64"/>
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<port type="output" prefix="d_out" size="64"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
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</circuit_model>
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</circuit_model>
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<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
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<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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@ -86,7 +86,7 @@
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-->
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-->
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<architecture>
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<architecture>
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<!--
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<!--
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ODIN II specific config begins
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ODIN II specific config begins
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@ -170,7 +170,7 @@
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</measure>
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</measure>
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<stimulate>
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<stimulate>
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<!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
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<!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
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<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"><!--frequency modified to speedup the fpga programing-->
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<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <!--frequency modified to speedup the fpga programing-->
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<rise slew_time="20e-12" slew_type="abs"/>
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<rise slew_time="20e-12" slew_type="abs"/>
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<fall slew_time="20e-12" slew_type="abs"/>
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<fall slew_time="20e-12" slew_type="abs"/>
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</clock>
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</clock>
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@ -180,7 +180,7 @@
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</input>
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</input>
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</stimulate>
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</stimulate>
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</parameters>
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</parameters>
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<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
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<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
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<transistors pn_ratio="2" model_ref="M">
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<transistors pn_ratio="2" model_ref="M">
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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@ -210,7 +210,7 @@
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10e-12
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10e-12
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</delay_matrix>
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</delay_matrix>
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</circuit_model>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0" >
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<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -221,7 +221,7 @@
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10e-12
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10e-12
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</delay_matrix>
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</delay_matrix>
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</circuit_model>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0" >
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<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -232,7 +232,7 @@
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10e-12
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10e-12
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</delay_matrix>
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</delay_matrix>
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</circuit_model>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0" >
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<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -243,7 +243,7 @@
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10e-12
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10e-12
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</delay_matrix>
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</delay_matrix>
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</circuit_model>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0" >
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<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
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<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -289,7 +289,8 @@
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<output_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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@ -297,7 +298,8 @@
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<output_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
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<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="output" prefix="out" size="1"/>
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</circuit_model>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<pass_gate_logic circuit_model_name="TGATEX1"/>
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<pass_gate_logic circuit_model_name="TGATEX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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</circuit_model>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<design_technology type="cmos" fracturable_lut="true"/>
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@ -372,19 +374,19 @@
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
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<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<input_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<output_buffer exist="on" circuit_model_name="INV1X"/>
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<pass_gate_logic circuit_model_name="TGATEX1"/>
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<pass_gate_logic circuit_model_name="TGATEX1"/>
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<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
|
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
|
||||||
<port type="input" prefix="D" size="1"/>
|
<port type="input" prefix="D" size="1"/>
|
||||||
<port type="output" prefix="Q" size="1"/>
|
<port type="output" prefix="Q" size="1"/>
|
||||||
<port type="output" prefix="Qb" size="1"/>
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
|
|
@ -393,21 +395,21 @@
|
||||||
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
|
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
|
||||||
<port type="input" prefix="outpad" size="1"/>
|
<port type="input" prefix="outpad" size="1"/>
|
||||||
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
|
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
|
||||||
<port type="output" prefix="inpad" size="1"/>
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<!-- Hard logic definition for heterogenous blocks -->
|
<!-- Hard logic definition for heterogenous blocks -->
|
||||||
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
|
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
<port type="input" prefix="a" size="1"/>
|
<port type="input" prefix="a" size="1"/>
|
||||||
<port type="input" prefix="b" size="1"/>
|
<port type="input" prefix="b" size="1"/>
|
||||||
<port type="input" prefix="cin" size="1"/>
|
<port type="input" prefix="cin" size="1"/>
|
||||||
<port type="output" prefix="sumout" size="1"/>
|
<port type="output" prefix="sumout" size="1"/>
|
||||||
<port type="output" prefix="cout" size="1"/>
|
<port type="output" prefix="cout" size="1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
|
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||||
|
|
@ -441,7 +443,7 @@
|
||||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||||
-->
|
-->
|
||||||
<area grid_logic_tile_area="0"/>
|
<area grid_logic_tile_area="0"/>
|
||||||
<sram area="6">
|
<sram area="6">
|
||||||
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
|
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
|
||||||
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
|
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
|
||||||
|
|
@ -460,7 +462,7 @@
|
||||||
</switch>
|
</switch>
|
||||||
</cblocks>
|
</cblocks>
|
||||||
<switchlist>
|
<switchlist>
|
||||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||||
|
|
@ -508,7 +510,7 @@
|
||||||
|
|
||||||
<!-- Define I/O pads begin -->
|
<!-- Define I/O pads begin -->
|
||||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||||
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
|
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
|
||||||
<input name="outpad" num_pins="1"/>
|
<input name="outpad" num_pins="1"/>
|
||||||
<output name="inpad" num_pins="1"/>
|
<output name="inpad" num_pins="1"/>
|
||||||
|
|
@ -579,8 +581,8 @@
|
||||||
<!-- Define I/O pads ends -->
|
<!-- Define I/O pads ends -->
|
||||||
|
|
||||||
|
|
||||||
<!-- Define general purpose logic block (CLB) begin -->
|
<!-- Define general purpose logic block (CLB) begin -->
|
||||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||||
|
|
@ -589,121 +591,121 @@
|
||||||
assume, but note that the total routing area really includes the crossbar, which would push
|
assume, but note that the total routing area really includes the crossbar, which would push
|
||||||
routing area up significantly, we estimate into the ~70% range.
|
routing area up significantly, we estimate into the ~70% range.
|
||||||
-->
|
-->
|
||||||
<pb_type name="clb" area="11388">
|
<pb_type name="clb" area="11388">
|
||||||
<input name="I0" num_pins="10" equivalent="true"/>
|
<input name="I0" num_pins="10" equivalent="true"/>
|
||||||
<input name="I1" num_pins="10" equivalent="true"/>
|
<input name="I1" num_pins="10" equivalent="true"/>
|
||||||
<input name="I2" num_pins="10" equivalent="true"/>
|
<input name="I2" num_pins="10" equivalent="true"/>
|
||||||
<input name="I3" num_pins="10" equivalent="true"/>
|
<input name="I3" num_pins="10" equivalent="true"/>
|
||||||
|
<input name="cin" num_pins="1"/>
|
||||||
|
<input name="cin_trick" num_pins="1"/>
|
||||||
|
<input name="regin" num_pins="1"/>
|
||||||
|
<output name="O" num_pins="20" equivalent="false"/>
|
||||||
|
<output name="cout" num_pins="1"/>
|
||||||
|
<output name="regout" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
|
||||||
|
<!-- Describe fracturable logic element.
|
||||||
|
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||||
|
The outputs of the fracturable logic element can be optionally registered
|
||||||
|
-->
|
||||||
|
<pb_type name="fle" num_pb="10" physical_mode_name="fle_phy" idle_mode_name="n2_lut5">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<input name="cin_trick" num_pins="1"/>
|
|
||||||
<input name="regin" num_pins="1"/>
|
<input name="regin" num_pins="1"/>
|
||||||
<output name="O" num_pins="20" equivalent="false"/>
|
<output name="out" num_pins="2"/>
|
||||||
<output name="cout" num_pins="1"/>
|
<output name="cout" num_pins="1"/>
|
||||||
<output name="regout" num_pins="1"/>
|
<output name="regout" num_pins="1"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<clock name="clk" num_pins="1"/>
|
||||||
|
|
||||||
<!-- Describe fracturable logic element.
|
<mode name="fle_phy" disabled_in_packing="true">
|
||||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
<!--pb_type name="fle_phy" num_pb="1" circuit_model_name="fle_phy">
|
||||||
The outputs of the fracturable logic element can be optionally registered
|
|
||||||
-->
|
|
||||||
<pb_type name="fle" num_pb="10" physical_mode_name="fle_phy" idle_mode_name="n2_lut5">
|
|
||||||
<input name="in" num_pins="6"/>
|
|
||||||
<input name="cin" num_pins="1"/>
|
|
||||||
<input name="regin" num_pins="1"/>
|
|
||||||
<output name="out" num_pins="2"/>
|
|
||||||
<output name="cout" num_pins="1"/>
|
|
||||||
<output name="regout" num_pins="1"/>
|
|
||||||
<clock name="clk" num_pins="1"/>
|
|
||||||
|
|
||||||
<mode name="fle_phy" disabled_in_packing="true">
|
|
||||||
<!--pb_type name="fle_phy" num_pb="1" circuit_model_name="fle_phy">
|
|
||||||
<input name="in" num_pins="6"/>
|
<input name="in" num_pins="6"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<output name="cout" num_pins="2"/>
|
<output name="cout" num_pins="2"/>
|
||||||
<clock name="clk" num_pins="1"/-->
|
<clock name="clk" num_pins="1"/-->
|
||||||
<pb_type name="frac_logic" num_pb="1">
|
<pb_type name="frac_logic" num_pb="1">
|
||||||
<input name="in" num_pins="6"/>
|
<input name="in" num_pins="6"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<input name="regin" num_pins="1"/>
|
<input name="regin" num_pins="1"/>
|
||||||
<input name="regchain" num_pins="1"/>
|
<input name="regchain" num_pins="1"/>
|
||||||
<output name="out" num_pins="2"/>
|
<output name="out" num_pins="2"/>
|
||||||
<output name="cout" num_pins="1"/>
|
<output name="cout" num_pins="1"/>
|
||||||
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" circuit_model_name="frac_lut6">
|
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" circuit_model_name="frac_lut6">
|
||||||
<input name="in" num_pins="6"/>
|
<input name="in" num_pins="6"/>
|
||||||
<output name="lut4_out" num_pins="4"/>
|
<output name="lut4_out" num_pins="4"/>
|
||||||
<output name="lut5_out" num_pins="2"/>
|
<output name="lut5_out" num_pins="2"/>
|
||||||
<output name="lut6_out" num_pins="1"/>
|
<output name="lut6_out" num_pins="1"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" circuit_model_name="adder">
|
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" circuit_model_name="adder">
|
||||||
<input name="a" num_pins="1"/>
|
<input name="a" num_pins="1"/>
|
||||||
<input name="b" num_pins="1"/>
|
<input name="b" num_pins="1"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<output name="cout" num_pins="1"/>
|
<output name="cout" num_pins="1"/>
|
||||||
<output name="sumout" num_pins="1"/>
|
<output name="sumout" num_pins="1"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
|
<direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
|
||||||
<direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
|
<direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
|
||||||
<direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
|
<direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
|
||||||
<direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
|
<direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
|
||||||
<direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
|
<direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
|
||||||
<direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
|
<direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
|
||||||
<direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
|
<direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
|
||||||
<direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
|
<direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
|
||||||
<mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
|
<mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
|
||||||
</mux>
|
</mux>
|
||||||
<mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
|
<mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
|
||||||
</mux>
|
</mux>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" circuit_model_name="static_dff">
|
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" circuit_model_name="static_dff">
|
||||||
<input name="D" num_pins="1" port_class="D"/>
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
<output name="Q" num_pins="1" port_class="Q"/>
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
|
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
|
||||||
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
|
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
|
<complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
|
||||||
<direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
|
<direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
|
||||||
<direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
|
<direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
|
||||||
<direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
|
<direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
|
||||||
<direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
|
<direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
|
||||||
<direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
|
<direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
|
||||||
<direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
|
<direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
|
||||||
<direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
|
<direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
|
||||||
<direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
|
<direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
|
||||||
<mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
|
<mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
|
||||||
</mux>
|
</mux>
|
||||||
<mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
|
<mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
|
||||||
</mux>
|
</mux>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</mode>
|
</mode>
|
||||||
<mode name="n2_lut5">
|
<mode name="n2_lut5">
|
||||||
<!-- multi-mode support -->
|
<!-- multi-mode support -->
|
||||||
<pb_type name="lut5inter" num_pb="1">
|
<pb_type name="lut5inter" num_pb="1">
|
||||||
|
<input name="in" num_pins="5"/>
|
||||||
|
<input name="cin" num_pins="1"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<output name="cout" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="ble5" num_pb="2" idle_mode_name="blut5">
|
||||||
<input name="in" num_pins="5"/>
|
<input name="in" num_pins="5"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<output name="out" num_pins="2"/>
|
<output name="out" num_pins="1"/>
|
||||||
<output name="cout" num_pins="1"/>
|
<output name="cout" num_pins="1"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<clock name="clk" num_pins="1"/>
|
||||||
<pb_type name="ble5" num_pb="2" idle_mode_name="blut5">
|
<mode name="blut5">
|
||||||
<input name="in" num_pins="5"/>
|
<pb_type name="flut5" num_pb="1">
|
||||||
<input name="cin" num_pins="1"/>
|
<input name="in" num_pins="5"/>
|
||||||
<output name="out" num_pins="1"/>
|
<output name="out" num_pins="1"/>
|
||||||
<output name="cout" num_pins="1"/>
|
<clock name="clk" num_pins="1"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<!-- Regular LUT mode -->
|
||||||
<mode name="blut5">
|
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5">
|
||||||
<pb_type name="flut5" num_pb="1">
|
<input name="in" num_pins="5" port_class="lut_in" physical_mode_pin="in[5:0]"/>
|
||||||
<input name="in" num_pins="5"/>
|
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
|
||||||
<output name="out" num_pins="1"/>
|
<!-- LUT timing using delay matrix -->
|
||||||
<clock name="clk" num_pins="1"/>
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
<!-- Regular LUT mode -->
|
|
||||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5">
|
|
||||||
<input name="in" num_pins="5" port_class="lut_in" physical_mode_pin="in[5:0]"/>
|
|
||||||
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
|
|
||||||
<!-- LUT timing using delay matrix -->
|
|
||||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
|
||||||
we instead take the average of these numbers to get more stable results
|
we instead take the average of these numbers to get more stable results
|
||||||
82e-12
|
82e-12
|
||||||
173e-12
|
173e-12
|
||||||
|
|
@ -711,161 +713,161 @@
|
||||||
263e-12
|
263e-12
|
||||||
398e-12
|
398e-12
|
||||||
-->
|
-->
|
||||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||||
255e-12
|
255e-12
|
||||||
255e-12
|
255e-12
|
||||||
255e-12
|
255e-12
|
||||||
255e-12
|
255e-12
|
||||||
255e-12
|
255e-12
|
||||||
</delay_matrix>
|
</delay_matrix>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
|
|
||||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
|
||||||
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
||||||
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
||||||
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
||||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
|
||||||
<direct name="direct1" input="flut5.in" output="lut5.in"/>
|
|
||||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
|
||||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
|
||||||
</direct>
|
|
||||||
<direct name="direct3" input="flut5.clk" output="ff.clk"/>
|
|
||||||
<mux name="mux1" input="ff.Q lut5.out" output="flut5.out" spice_model_sram_offset="0">
|
|
||||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
|
|
||||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
|
|
||||||
</mux>
|
|
||||||
</interconnect>
|
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="ble5.in" output="flut5.in"/>
|
<direct name="direct1" input="flut5.in" output="lut5.in"/>
|
||||||
<direct name="direct2" input="ble5.clk" output="flut5.clk"/>
|
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||||
<direct name="direct3" input="flut5.out" output="ble5.out"/>
|
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="direct3" input="flut5.clk" output="ff.clk"/>
|
||||||
|
<mux name="mux1" input="ff.Q lut5.out" output="flut5.out" spice_model_sram_offset="0">
|
||||||
|
<delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
|
||||||
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
|
||||||
|
</mux>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</mode>
|
</pb_type>
|
||||||
<mode name="arithmetic">
|
<interconnect>
|
||||||
<pb_type name="arithmetic" num_pb="1">
|
<direct name="direct1" input="ble5.in" output="flut5.in"/>
|
||||||
<input name="in" num_pins="4"/>
|
<direct name="direct2" input="ble5.clk" output="flut5.clk"/>
|
||||||
<input name="cin" num_pins="1"/>
|
<direct name="direct3" input="flut5.out" output="ble5.out"/>
|
||||||
<output name="out" num_pins="1"/>
|
</interconnect>
|
||||||
<output name="cout" num_pins="1"/>
|
</mode>
|
||||||
<clock name="clk" num_pins="1"/>
|
<mode name="arithmetic">
|
||||||
<!-- Special dual-LUT mode that drives adder only -->
|
<pb_type name="arithmetic" num_pb="1">
|
||||||
<pb_type name="lut4" blif_model=".names" num_pb="2" class="lut" mode_bits="11" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.25">
|
<input name="in" num_pins="4"/>
|
||||||
<input name="in" num_pins="4" port_class="lut_in" physical_mode_pin="in[4:0]"/>
|
<input name="cin" num_pins="1"/>
|
||||||
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
|
<output name="out" num_pins="1"/>
|
||||||
<!-- LUT timing using delay matrix -->
|
<output name="cout" num_pins="1"/>
|
||||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<!-- Special dual-LUT mode that drives adder only -->
|
||||||
|
<pb_type name="lut4" blif_model=".names" num_pb="2" class="lut" mode_bits="11" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.25">
|
||||||
|
<input name="in" num_pins="4" port_class="lut_in" physical_mode_pin="in[4:0]"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
we instead take the average of these numbers to get more stable results
|
we instead take the average of these numbers to get more stable results
|
||||||
82e-12
|
82e-12
|
||||||
173e-12
|
173e-12
|
||||||
261e-12
|
261e-12
|
||||||
263e-12
|
263e-12
|
||||||
-->
|
-->
|
||||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||||
202e-12
|
202e-12
|
||||||
202e-12
|
202e-12
|
||||||
202e-12
|
202e-12
|
||||||
202e-12
|
202e-12
|
||||||
</delay_matrix>
|
</delay_matrix>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<pb_type name="adder" blif_model=".subckt adder" num_pb="1" physical_pb_type_name="adder_phy">
|
<pb_type name="adder" blif_model=".subckt adder" num_pb="1" physical_pb_type_name="adder_phy">
|
||||||
<input name="a" num_pins="1" physical_mode_pin="a"/>
|
<input name="a" num_pins="1" physical_mode_pin="a"/>
|
||||||
<input name="b" num_pins="1" physical_mode_pin="b"/>
|
<input name="b" num_pins="1" physical_mode_pin="b"/>
|
||||||
<input name="cin" num_pins="1" physical_mode_pin="cin"/>
|
<input name="cin" num_pins="1" physical_mode_pin="cin"/>
|
||||||
<output name="cout" num_pins="1" physical_mode_pin="cout"/>
|
<output name="cout" num_pins="1" physical_mode_pin="cout"/>
|
||||||
<output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
|
<output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
|
||||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
||||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
||||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
||||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
||||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
||||||
<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
|
<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
|
||||||
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
||||||
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
||||||
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
||||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
|
||||||
<direct name="clock" input="arithmetic.clk" output="ff.clk"/>
|
|
||||||
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
|
|
||||||
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
|
|
||||||
<direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
|
|
||||||
</direct>
|
|
||||||
<direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
|
|
||||||
</direct>
|
|
||||||
<direct name="add_to_ff" input="adder.sumout" output="ff.D">
|
|
||||||
<pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
|
|
||||||
</direct>
|
|
||||||
<direct name="carry_in" input="arithmetic.cin" output="adder.cin">
|
|
||||||
<pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
|
|
||||||
</direct>
|
|
||||||
<direct name="carry_out" input="adder.cout" output="arithmetic.cout">
|
|
||||||
<pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
|
|
||||||
</direct>
|
|
||||||
<mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
|
|
||||||
<delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
|
|
||||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
|
|
||||||
</mux>
|
|
||||||
</interconnect>
|
|
||||||
</pb_type>
|
</pb_type>
|
||||||
|
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
|
<direct name="clock" input="arithmetic.clk" output="ff.clk"/>
|
||||||
<direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
|
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
|
||||||
<pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
|
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
|
||||||
|
<direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
|
<direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
|
||||||
<pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
|
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
|
<direct name="add_to_ff" input="adder.sumout" output="ff.D">
|
||||||
<direct name="direct3" input="arithmetic.out" output="ble5.out"/>
|
<pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="carry_in" input="arithmetic.cin" output="adder.cin">
|
||||||
|
<pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="carry_out" input="adder.cout" output="arithmetic.cout">
|
||||||
|
<pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
|
||||||
|
</direct>
|
||||||
|
<mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
|
||||||
|
<delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
|
||||||
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
|
||||||
|
</mux>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</mode>
|
</pb_type>
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
<direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
|
||||||
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
<direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
|
||||||
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
<pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
|
||||||
<direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
|
</direct>
|
||||||
<pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/>
|
<direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
|
||||||
</direct>
|
<pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
|
||||||
<direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
|
</direct>
|
||||||
<pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/>
|
<direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
|
||||||
</direct>
|
<direct name="direct3" input="arithmetic.out" output="ble5.out"/>
|
||||||
<direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
|
</interconnect>
|
||||||
<pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
|
</mode>
|
||||||
</direct>
|
|
||||||
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
|
||||||
</interconnect>
|
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
||||||
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
||||||
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
||||||
<direct name="carry_in" input="fle.cin" output="lut5inter.cin">
|
<direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
|
||||||
<pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
|
<pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/>
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="carry_out" input="lut5inter.cout" output="fle.cout">
|
<direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
|
||||||
<pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/>
|
<pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/>
|
||||||
</direct>
|
</direct>
|
||||||
|
<direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
|
||||||
|
<pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
|
||||||
|
</direct>
|
||||||
|
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</mode> <!-- n2_lut5 -->
|
</pb_type>
|
||||||
<mode name="n1_lut6">
|
<interconnect>
|
||||||
<pb_type name="ble6" num_pb="1">
|
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
||||||
<input name="in" num_pins="6"/>
|
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
||||||
<output name="out" num_pins="1"/>
|
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
<direct name="carry_in" input="fle.cin" output="lut5inter.cin">
|
||||||
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" mode_bits="00" physical_pb_type_name="frac_lut6" spice_model_sram_offset="0">
|
<pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
|
||||||
<input name="in" num_pins="6" port_class="lut_in" physical_mode_pin="in[5:0]"/>
|
</direct>
|
||||||
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut6_out[0]"/>
|
<direct name="carry_out" input="lut5inter.cout" output="fle.cout">
|
||||||
<!-- LUT timing using delay matrix -->
|
<pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/>
|
||||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
</direct>
|
||||||
|
</interconnect>
|
||||||
|
</mode> <!-- n2_lut5 -->
|
||||||
|
<mode name="n1_lut6">
|
||||||
|
<pb_type name="ble6" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" mode_bits="00" physical_pb_type_name="frac_lut6" spice_model_sram_offset="0">
|
||||||
|
<input name="in" num_pins="6" port_class="lut_in" physical_mode_pin="in[5:0]"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut6_out[0]"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
we instead take the average of these numbers to get more stable results
|
we instead take the average of these numbers to get more stable results
|
||||||
82e-12
|
82e-12
|
||||||
173e-12
|
173e-12
|
||||||
|
|
@ -874,75 +876,75 @@
|
||||||
398e-12
|
398e-12
|
||||||
397e-12
|
397e-12
|
||||||
-->
|
-->
|
||||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||||
261e-12
|
261e-12
|
||||||
261e-12
|
261e-12
|
||||||
261e-12
|
261e-12
|
||||||
261e-12
|
261e-12
|
||||||
261e-12
|
261e-12
|
||||||
261e-12
|
261e-12
|
||||||
</delay_matrix>
|
</delay_matrix>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1">
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1">
|
||||||
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
||||||
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
||||||
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
||||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
|
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
|
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
|
||||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
|
||||||
</mux>
|
</mux>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||||||
|
<direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode> <!-- n1_lut6 -->
|
||||||
|
<mode name="shift_register">
|
||||||
|
<pb_type name="ble_shift" num_pb="1">
|
||||||
|
<input name="in" num_pins="1"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<output name="regout" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop" physical_pb_type_name="ff_phy">
|
||||||
|
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<interconnect>
|
<interconnect>
|
||||||
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
<direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
|
||||||
<direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
|
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
|
||||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
<pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
|
||||||
|
<direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
|
||||||
|
<direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
|
||||||
|
<complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
</mode> <!-- n1_lut6 -->
|
</pb_type>
|
||||||
<mode name="shift_register">
|
<interconnect>
|
||||||
<pb_type name="ble_shift" num_pb="1">
|
<direct name="direct1" input="fle.regin" output="ble_shift.in"/>
|
||||||
<input name="in" num_pins="1"/>
|
<direct name="direct2" input="ble_shift.out" output="fle.out"/>
|
||||||
<output name="out" num_pins="2"/>
|
<direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
|
||||||
<output name="regout" num_pins="1"/>
|
<direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
|
||||||
<clock name="clk" num_pins="1"/>
|
</interconnect>
|
||||||
<pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop" physical_pb_type_name="ff_phy">
|
</mode> <!-- shift_register -->
|
||||||
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
|
</pb_type>
|
||||||
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
|
<interconnect>
|
||||||
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
|
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
|
||||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
|
||||||
<direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
|
|
||||||
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
|
|
||||||
<pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/>
|
|
||||||
</direct>
|
|
||||||
<direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
|
|
||||||
<direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
|
|
||||||
<direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
|
|
||||||
<complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
|
|
||||||
</interconnect>
|
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
|
||||||
<direct name="direct1" input="fle.regin" output="ble_shift.in"/>
|
|
||||||
<direct name="direct2" input="ble_shift.out" output="fle.out"/>
|
|
||||||
<direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
|
|
||||||
<direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
|
|
||||||
</interconnect>
|
|
||||||
</mode> <!-- shift_register -->
|
|
||||||
</pb_type>
|
|
||||||
<interconnect>
|
|
||||||
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
|
||||||
The delays below come from Stratix IV. the delay through a connection block
|
The delays below come from Stratix IV. the delay through a connection block
|
||||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||||
|
|
@ -951,82 +953,82 @@
|
||||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||||
to get the part that should be marked on the crossbar. -->
|
to get the part that should be marked on the crossbar. -->
|
||||||
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" circuit_model_name="mux_2level">
|
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" circuit_model_name="mux_2level">
|
||||||
<delay_constant max="90.2e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
|
<delay_constant max="90.2e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
|
||||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
|
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" circuit_model_name="mux_2level">
|
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" circuit_model_name="mux_2level">
|
||||||
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
|
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
|
||||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
|
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" circuit_model_name="mux_2level">
|
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" circuit_model_name="mux_2level">
|
||||||
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
|
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
|
||||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
|
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" circuit_model_name="mux_2level">
|
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" circuit_model_name="mux_2level">
|
||||||
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
|
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
|
||||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
|
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" circuit_model_name="mux_2level">
|
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" circuit_model_name="mux_2level">
|
||||||
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
|
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
|
||||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
|
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" circuit_model_name="mux_2level">
|
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" circuit_model_name="mux_2level">
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||||
</complete>
|
</complete>
|
||||||
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" circuit_model_name="mux_2level">
|
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" circuit_model_name="mux_2level">
|
||||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||||
<delay_constant max="0.16e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/>
|
<delay_constant max="0.16e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/>
|
||||||
<!--pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/-->
|
<!--pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/-->
|
||||||
<pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/>
|
<pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/>
|
||||||
</complete>
|
</complete>
|
||||||
|
|
||||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||||
naive specification).
|
naive specification).
|
||||||
-->
|
-->
|
||||||
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||||||
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||||||
|
|
||||||
<!-- Shift register links -->
|
<!-- Shift register links -->
|
||||||
<direct name="regin" input="clb.regin" output="fle[0:0].regin">
|
<direct name="regin" input="clb.regin" output="fle[0:0].regin">
|
||||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||||
<delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
<delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
||||||
<pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
<pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="regout" input="fle[9:9].regout" output="clb.regout">
|
<direct name="regout" input="fle[9:9].regout" output="clb.regout">
|
||||||
<pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
|
<pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
|
<direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
|
||||||
<pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
|
<pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
|
||||||
</direct>
|
</direct>
|
||||||
<!-- Carry chain links -->
|
<!-- Carry chain links -->
|
||||||
<direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
|
<direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
|
||||||
<pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
|
<pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
|
||||||
</direct>
|
</direct>
|
||||||
<direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
|
<direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
|
||||||
<pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
|
<pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
|
||||||
</direct>
|
</direct>
|
||||||
</interconnect>
|
</interconnect>
|
||||||
|
|
||||||
<fc default_in_type="frac" default_in_val="0.055" default_out_type="frac" default_out_val="0.10">
|
<fc default_in_type="frac" default_in_val="0.055" default_out_type="frac" default_out_val="0.10">
|
||||||
<pin name="cin" fc_type="frac" fc_val="0"/>
|
<pin name="cin" fc_type="frac" fc_val="0"/>
|
||||||
<pin name="cout" fc_type="frac" fc_val="0"/>
|
<pin name="cout" fc_type="frac" fc_val="0"/>
|
||||||
</fc>
|
</fc>
|
||||||
|
|
||||||
<pinlocations pattern="custom">
|
<pinlocations pattern="custom">
|
||||||
<loc side="top"> clb.cin clb.cin_trick clb.regin clb.clk </loc>
|
<loc side="top"> clb.cin clb.cin_trick clb.regin clb.clk </loc>
|
||||||
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
|
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
|
||||||
<loc side="bottom">clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
|
<loc side="bottom">clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
|
||||||
<loc side="left"></loc>
|
<loc side="left"></loc>
|
||||||
</pinlocations>
|
</pinlocations>
|
||||||
<gridlocations>
|
<gridlocations>
|
||||||
<loc type="fill" priority="1"/>
|
<loc type="fill" priority="1"/>
|
||||||
</gridlocations>
|
</gridlocations>
|
||||||
</pb_type>
|
</pb_type>
|
||||||
<!-- Define general purpose logic block (CLB) ends -->
|
<!-- Define general purpose logic block (CLB) ends -->
|
||||||
</complexblocklist>
|
</complexblocklist>
|
||||||
<power>
|
<power>
|
||||||
<local_interconnect C_wire="2.5e-10"/>
|
<local_interconnect C_wire="2.5e-10"/>
|
||||||
|
|
|
||||||
|
|
@ -290,7 +290,7 @@
|
||||||
<port type="sram" prefix="sram" size="1"/>
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
@ -342,7 +342,7 @@
|
||||||
<port type="sram" prefix="sram" size="16"/>
|
<port type="sram" prefix="sram" size="16"/>
|
||||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
|
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v" >
|
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v" >
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
@ -350,7 +350,7 @@
|
||||||
<port type="input" prefix="in" size="1"/>
|
<port type="input" prefix="in" size="1"/>
|
||||||
<port type="output" prefix="out" size="2"/>
|
<port type="output" prefix="out" size="2"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
|
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
@ -362,7 +362,7 @@
|
||||||
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
|
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
@ -373,7 +373,7 @@
|
||||||
<port type="output" prefix="Qb" size="1"/>
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
@ -384,7 +384,7 @@
|
||||||
<port type="output" prefix="inpad" size="1"/>
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
</circuit_model>
|
</circuit_model>
|
||||||
<!-- Hard logic definition for heterogenous blocks -->
|
<!-- Hard logic definition for heterogenous blocks -->
|
||||||
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
|
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
|
||||||
<design_technology type="cmos"/>
|
<design_technology type="cmos"/>
|
||||||
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
<input_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
<output_buffer exist="on" circuit_model_name="INVTX1"/>
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue