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added tileable routing chanW adaption to fixed W router

This commit is contained in:
tangxifan 2019-07-03 14:29:50 -06:00
parent 45b00e0881
commit 4f3cb0bdf3
2 changed files with 16 additions and 1 deletions
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2
fpga_flow/scripts/fpga_flow.pl
View File

@ -1474,7 +1474,7 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $)
my ($chan_width_opt) = ("");
if (($fix_chan_width > 0)||($fix_chan_width == 0)) {
$chan_width_opt = "-route_chan_width $fix_chan_width";
$chan_width_opt = "--route_chan_width $fix_chan_width";
}
if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) {
$chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width";

15
vpr7_x2p/vpr/SRC/base/place_and_route.c
View File

@ -153,6 +153,21 @@ void place_and_route(enum e_operation operation,
}
/* Other constraints can be left to rr_graph to check since this is one pass routing */
/* Xifan Tang: W estimation for tileable routing architecture */
/* Build the segment inf vector */
std::vector<t_segment_inf> segment_vec;
for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) {
segment_vec.push_back(segment_inf[iseg]);
}
if (TRUE == router_opts.use_tileable_route_chan_width) {
int adapted_W = adapt_to_tileable_route_chan_width(width_fac, segment_vec);
vpr_printf(TIO_MESSAGE_INFO,
"Adapt routing channel width (%d) to be tileable: %d\n",
width_fac, adapted_W);
width_fac = adapted_W;
}
/* Allocate the major routing structures. */
clb_opins_used_locally = alloc_route_structs();