From 4f3cb0bdf34c11a76b231c18d65d6a54e16174d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 14:29:50 -0600 Subject: [PATCH] added tileable routing chanW adaption to fixed W router --- fpga_flow/scripts/fpga_flow.pl | 2 +- vpr7_x2p/vpr/SRC/base/place_and_route.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 23cb76067..6474004a3 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1474,7 +1474,7 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) my ($chan_width_opt) = (""); if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "-route_chan_width $fix_chan_width"; + $chan_width_opt = "--route_chan_width $fix_chan_width"; } if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index 1e2bad1f2..8c1d410a2 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -153,6 +153,21 @@ void place_and_route(enum e_operation operation, } /* Other constraints can be left to rr_graph to check since this is one pass routing */ + /* Xifan Tang: W estimation for tileable routing architecture */ + /* Build the segment inf vector */ + std::vector segment_vec; + for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { + segment_vec.push_back(segment_inf[iseg]); + } + + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(width_fac, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + width_fac, adapted_W); + width_fac = adapted_W; + } + /* Allocate the major routing structures. */ clb_opins_used_locally = alloc_route_structs();