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[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank

This commit is contained in:
tangxifan 2021-09-29 22:32:45 -07:00
parent 2d4c200d58
commit 4d8019b7c1
2 changed files with 25 additions and 9 deletions
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24
openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
View File

@ -249,8 +249,12 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
}
}
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
bl_addr_port_info.set_width(1); /* Deposit minimum width */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
size_t num_bls = compute_memory_bank_regional_num_bls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model());
bl_addr_port_info.set_width(std::max(num_bls, bl_addr_port_info.get_width()));
}
}
/* For different WL control protocol, the address ports are different
@ -275,8 +279,12 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
}
}
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
wl_addr_port_info.set_width(1); /* Deposit minimum width */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
size_t num_wls = compute_memory_bank_regional_num_wls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model());
wl_addr_port_info.set_width(std::max(num_wls, wl_addr_port_info.get_width()));
}
}
/* Reserve bits before build-up */
@ -297,26 +305,30 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
/* Find the BL/WL port (different region may have different sizes of BL/WLs) */
ModulePortId cur_bl_addr_port;
BasicPort cur_bl_addr_port_info;
if (BLWL_PROTOCOL_DECODER == config_protocol.bl_protocol_type()) {
cur_bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
cur_bl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_BL_PORT_NAME), config_region));
cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
cur_bl_addr_port_info.set_width(compute_memory_bank_regional_num_bls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model()));
}
BasicPort cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
ModulePortId cur_wl_addr_port;
BasicPort cur_wl_addr_port_info;
if (BLWL_PROTOCOL_DECODER == config_protocol.wl_protocol_type()) {
cur_wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()) {
cur_wl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_WL_PORT_NAME), config_region));
cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
cur_wl_addr_port_info.set_width(compute_memory_bank_regional_num_wls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model()));
}
BasicPort cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
/**************************************************************
* Precompute the BLs and WLs distribution across the FPGA fabric

10
openfpga/src/utils/memory_utils.cpp
View File

@ -447,11 +447,15 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(const Confi
|| CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
VTR_ASSERT(2 <= curr_region_num_config_child);
num_child_to_skip = 2;
/* If flatten bus is used, BL/WL may not need decoders */
if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
/* - If flatten bus is used, BL/WL may not need decoders
* - If shift registers are used, BL/WLs do not need decoders. And shift registers are not counted as configurable children
*/
if ( BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()
|| BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type() ) {
num_child_to_skip--;
}
if (BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()) {
if ( BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()
|| BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type() ) {
num_child_to_skip--;
}
}