From 4d8019b7c1c1d4b5020570ce041d069e5cca23e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Sep 2021 22:32:45 -0700
Subject: [PATCH] [FPGA-Bitstream] Bug fix in bitstream generator for
 shift-register-based memory bank

---
 .../build_fabric_bitstream_memory_bank.cpp    | 24 ++++++++++++++-----
 openfpga/src/utils/memory_utils.cpp           | 10 +++++---
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
index 998b3960b..7742b9bf9 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
@@ -249,8 +249,12 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
       }
     }
   } else {
-    /* TODO */
     VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
+    bl_addr_port_info.set_width(1); /* Deposit minimum width */
+    for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
+      size_t num_bls = compute_memory_bank_regional_num_bls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model());
+      bl_addr_port_info.set_width(std::max(num_bls, bl_addr_port_info.get_width()));
+    }
   }
 
   /* For different WL control protocol, the address ports are different 
@@ -275,8 +279,12 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
       }
     }
   } else {
-    /* TODO */
     VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
+    wl_addr_port_info.set_width(1); /* Deposit minimum width */
+    for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
+      size_t num_wls = compute_memory_bank_regional_num_wls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model());
+      wl_addr_port_info.set_width(std::max(num_wls, wl_addr_port_info.get_width()));
+    }
   }
 
   /* Reserve bits before build-up */
@@ -297,26 +305,30 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
     
     /* Find the BL/WL port (different region may have different sizes of BL/WLs) */
     ModulePortId cur_bl_addr_port;
+    BasicPort cur_bl_addr_port_info;
     if (BLWL_PROTOCOL_DECODER == config_protocol.bl_protocol_type()) {
       cur_bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
+      cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
     } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
       cur_bl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_BL_PORT_NAME), config_region));
+      cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
     } else {
-      /* TODO */
       VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
+      cur_bl_addr_port_info.set_width(compute_memory_bank_regional_num_bls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model()));
     }
-    BasicPort cur_bl_addr_port_info = module_manager.module_port(top_module, cur_bl_addr_port);
 
     ModulePortId cur_wl_addr_port;
+    BasicPort cur_wl_addr_port_info;
     if (BLWL_PROTOCOL_DECODER == config_protocol.wl_protocol_type()) {
       cur_wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
+      cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
     } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()) {
       cur_wl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_WL_PORT_NAME), config_region));
+      cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
     } else {
-      /* TODO */
       VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
+      cur_wl_addr_port_info.set_width(compute_memory_bank_regional_num_wls(module_manager, top_module, config_region, circuit_lib, config_protocol.memory_model()));
     }
-    BasicPort cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
 
     /************************************************************** 
      * Precompute the BLs and WLs distribution across the FPGA fabric
diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp
index 71c2c60ef..8da43d02b 100644
--- a/openfpga/src/utils/memory_utils.cpp
+++ b/openfpga/src/utils/memory_utils.cpp
@@ -447,11 +447,15 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(const Confi
       || CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
     VTR_ASSERT(2 <= curr_region_num_config_child);
     num_child_to_skip = 2;
-    /* If flatten bus is used, BL/WL may not need decoders */
-    if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
+    /* - If flatten bus is used, BL/WL may not need decoders
+     * - If shift registers are used, BL/WLs do not need decoders. And shift registers are not counted as configurable children 
+     */
+    if ( BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()
+      || BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type() ) {
       num_child_to_skip--;
     }
-    if (BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()) {
+    if ( BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()
+      || BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type() ) {
       num_child_to_skip--;
     }
   }