riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed

This commit is contained in:
tangxifan 2021-02-24 11:51:10 -07:00
parent 38f08588c8
commit 4c2a88e27f
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -206,9 +206,9 @@
<!-- A dummy model to include the adder_lut verilog code in testbench netlists <!-- A dummy model to include the adder_lut verilog code in testbench netlists
so that HDL simulation can be run when adder lut is used in users' implementations so that HDL simulation can be run when adder lut is used in users' implementations
--> -->
<circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v"> <!--circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v">
<design_technology type="cmos" topology="inverter" size="1"/> <design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model> </circuit_model-->
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/> <organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>