From 4c2a88e27f064ecb03bf05e8541265cd85974d3f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 24 Feb 2021 11:51:10 -0700
Subject: [PATCH] [Arch] Comment out yosys tech lib Verilog to see if it caused
 CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is
 low; Local test with iVerilog v10.3 passed

---
 ...r_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 0198e5c24..d40e7bea2 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -206,9 +206,9 @@
     <!-- A dummy model to include the adder_lut verilog code in testbench netlists
          so that HDL simulation can be run when adder lut is used in users' implementations
      -->
-    <circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v">
+    <!--circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v">
       <design_technology type="cmos" topology="inverter" size="1"/>
-    </circuit_model>
+    </circuit_model-->
   </circuit_library>
   <configuration_protocol>
     <organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>