add configuration chain sdc writer
This commit is contained in:
tangxifan
parent
dad99d13a2
commit
4c0953415b
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@ -15,6 +15,7 @@
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#include "circuit_library_utils.h"
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#include "pnr_sdc_writer.h"
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#include "analysis_sdc_writer.h"
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#include "configuration_chain_sdc_writer.h"
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#include "openfpga_sdc.h"
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/* Include global variables of VPR */
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@ -102,6 +103,41 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* A wrapper function to call the PnR SDC generator on configuration chain
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* of FPGA-SDC
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*******************************************************************/
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int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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/* If the configuration protocol is not a configuration chain, we will not write anything */
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if (CONFIG_MEM_SCAN_CHAIN != openfpga_ctx.arch().config_protocol.type()) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Configuration protocol is %s. Expected %s to write SDC!\n",
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CONFIG_PROTOCOL_TYPE_STRING[openfpga_ctx.arch().config_protocol.type()],
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CONFIG_PROTOCOL_TYPE_STRING[CONFIG_MEM_SCAN_CHAIN]);
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Get command options */
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_time_unit = cmd.option("time_unit");
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CommandOptionId opt_min_delay = cmd.option("min_delay");
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CommandOptionId opt_max_delay = cmd.option("max_delay");
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std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
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float time_unit = string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit));
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/* Write the SDC for configuration chain */
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print_pnr_sdc_constrain_configurable_chain(cmd_context.option_value(cmd, opt_output_dir),
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time_unit,
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std::stof(cmd_context.option_value(cmd, opt_max_delay)),
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std::stof(cmd_context.option_value(cmd, opt_min_delay)),
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openfpga_ctx.module_graph());
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* A wrapper function to call the analysis SDC generator of FPGA-SDC
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*******************************************************************/
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@ -18,6 +18,9 @@ namespace openfpga {
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int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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@ -80,6 +80,45 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC for configuration chain
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_configuration_chain_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_configuration_chain_sdc");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the SDC file to constrain configuration chain");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--time_unit' */
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CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s");
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shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
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/* Add an option '--min_delay' */
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CommandOptionId min_dly_opt = shell_cmd.add_option("min_delay", false, "Specify the minimum delay to be used.");
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shell_cmd.set_option_require_value(min_dly_opt, openfpga::OPT_STRING);
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/* Add an option '--max_delay' */
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CommandOptionId max_dly_opt = shell_cmd.add_option("max_delay", false, "Specify the maximum delay to be used.");
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shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING);
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/* Add command 'write_configuration_chain_sdc' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the configuration chain for FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(shell_cmd_id, write_configuration_chain_sdc);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC
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* - Add associated options
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@ -134,6 +173,16 @@ void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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openfpga_sdc_cmd_class,
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pnr_sdc_cmd_dependency);
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/********************************
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* Command 'write_configuration_chain_sdc'
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*/
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/* The 'write_configuration_chain_sdc' command should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> cc_sdc_cmd_dependency;
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cc_sdc_cmd_dependency.push_back(build_fabric_id);
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add_openfpga_write_configuration_chain_sdc_command(shell,
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openfpga_sdc_cmd_class,
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cc_sdc_cmd_dependency);
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/********************************
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* Command 'write_analysis_sdc'
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*/
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@ -0,0 +1,175 @@
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/********************************************************************
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* This file includes functions that print SDC (Synopsys Design Constraint)
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* files in physical design tools, i.e., Place & Route (PnR) tools
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* The SDC files are used to constrain the timing of configuration chain
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*
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* Note that this is different from the SDC to constrain VPR Place&Route
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* engine! These SDCs are designed for PnR to generate FPGA layouts!!!
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*******************************************************************/
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#include <ctime>
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#include <fstream>
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#include <iomanip>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_scale.h"
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "sdc_writer_utils.h"
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#include "configuration_chain_sdc_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print SDC commands to constrain the timing between outputs and inputs
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* of all the configurable memory modules
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*
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* |<------Max/Min delay-->|
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* | |
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* +------+ out in +------+
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* | CCFF |---------------------->| CCFF |
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* +------+ +------+
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*
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* This function will be executed in a recursive way,
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* using a Depth-First Search (DFS) strategy
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* It will iterate over all the configurable children under each module
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* and print a SDC command
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*
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*******************************************************************/
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static
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void rec_print_pnr_sdc_constrain_configurable_chain(std::fstream& fp,
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const float& tmax,
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const float& tmin,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_module_path,
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std::string& previous_module_path,
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ModuleId& previous_module) {
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/* For each configurable child, we will go one level down in priority */
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for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
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std::string child_module_path = parent_module_path;
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ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
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size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
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std::string child_instance_name;
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if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
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child_instance_name = generate_instance_name(module_manager.module_name(child_module_id), child_instance_id);
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} else {
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child_instance_name = module_manager.instance_name(parent_module, child_module_id, child_instance_id);
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}
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child_module_path += child_instance_name;
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child_module_path = format_dir_path(child_module_path);
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rec_print_pnr_sdc_constrain_configurable_chain(fp,
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tmax, tmin,
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module_manager,
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child_module_id,
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child_module_path,
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previous_module_path,
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previous_module);
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}
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/* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */
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if (0 < module_manager.configurable_children(parent_module).size()) {
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return;
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}
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/* Validate file stream */
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valid_file_stream(fp);
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/* Disable timing for each output port of this module */
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if (!previous_module_path.empty()) {
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bool first_port = true;
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for (const BasicPort& output_port : module_manager.module_ports_by_type(previous_module, ModuleManager::MODULE_OUTPUT_PORT)) {
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/* Only the first output port will be considered,
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* being consistent with build_memory_module.cpp:395
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*/
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if (false == first_port) {
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continue;
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}
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for (const BasicPort& input_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_INPUT_PORT)) {
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print_pnr_sdc_constrain_max_delay(fp,
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previous_module_path,
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generate_sdc_port(output_port),
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parent_module_path,
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generate_sdc_port(input_port),
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tmax);
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print_pnr_sdc_constrain_min_delay(fp,
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previous_module_path,
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generate_sdc_port(output_port),
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parent_module_path,
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generate_sdc_port(input_port),
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tmin);
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}
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first_port = false;
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}
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}
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/* Update previous module */
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previous_module_path = parent_module_path;
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previous_module = parent_module;
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}
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/********************************************************************
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* Break combinational loops in FPGA fabric, which mainly come from
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* configurable memory cells.
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* To handle this, we disable the outputs of memory cells
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*******************************************************************/
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void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
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const float& time_unit,
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const float& max_delay,
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const float& min_delay,
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const ModuleManager& module_manager) {
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/* Create the directory */
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create_directory(find_path_dir_name(sdc_fname));
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/* Start time count */
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std::string timer_message = std::string("Write SDC to constrain configurable chain for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Timing constraints for configurable chains used in PnR"));
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/* Print time unit for the SDC file */
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print_sdc_timescale(fp, time_unit_to_string(time_unit));
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
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std::string previous_module_path;
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ModuleId previous_module = ModuleId::INVALID();
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rec_print_pnr_sdc_constrain_configurable_chain(fp,
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max_delay/time_unit, min_delay/time_unit,
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module_manager, top_module,
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format_dir_path(module_manager.module_name(top_module)),
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previous_module_path,
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previous_module);
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/* Close file handler */
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fp.close();
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}
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} /* end namespace openfpga */
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@ -0,0 +1,26 @@
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#ifndef CONFIGURATION_CHAIN_SDC_WRITER_H
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#define CONFIGURATION_CHAIN_SDC_WRITER_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
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const float& time_unit,
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const float& max_delay,
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const float& min_delay,
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const ModuleManager& module_manager);
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} /* end namespace openfpga */
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#endif
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@ -95,14 +95,14 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
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fp << " -from ";
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if (!src_instance_name.empty()) {
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fp << src_instance_name << "/";
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fp << format_dir_path(src_instance_name);
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}
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fp << src_port_name;
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fp << " -to ";
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if (!des_instance_name.empty()) {
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fp << des_instance_name << "/";
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fp << format_dir_path(des_instance_name);
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}
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fp << des_port_name;
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@ -130,7 +130,7 @@ void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
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fp << " -from ";
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fp << "[get_pins -regexp \"";
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if (!src_instance_name.empty()) {
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fp << src_instance_name << "/";
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fp << format_dir_path(src_instance_name);
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}
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fp << src_port_name;
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@ -140,7 +140,7 @@ void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
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fp << "[get_pins -regexp \"";
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if (!des_instance_name.empty()) {
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fp << des_instance_name << "/";
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fp << format_dir_path(des_instance_name);
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}
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fp << des_port_name;
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@ -167,14 +167,14 @@ void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
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fp << " -from ";
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if (!src_instance_name.empty()) {
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fp << src_instance_name << "/";
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fp << format_dir_path(src_instance_name);
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}
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fp << src_port_name;
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fp << " -to ";
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if (!des_instance_name.empty()) {
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fp << des_instance_name << "/";
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fp << format_dir_path(des_instance_name);
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}
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fp << des_port_name;
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