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[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken

This commit is contained in:
tangxifan 2021-09-30 21:20:56 -07:00
parent 33972fc0ec
commit 4bdff1554d
2 changed files with 10 additions and 11 deletions
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4
openfpga/src/fabric/build_top_module_memory_bank.cpp
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@ -1199,6 +1199,8 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name);
BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port);
cur_sr_module_blwl_pin_id = cur_sr_module_blwl_pin_id % sr_module_blwl_port_info.get_width();
/* Create net */ /* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
sr_bank_module, sr_bank_instance, sr_bank_module, sr_bank_instance,
@ -1210,8 +1212,6 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
size_t sink_pin_id = sr_banks.shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id]; size_t sink_pin_id = sr_banks.shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
module_manager.add_module_net_sink(top_module, net, module_manager.add_module_net_sink(top_module, net,
child_module, child_instance, child_blwl_port, sink_pin_id); child_module, child_instance, child_blwl_port, sink_pin_id);
cur_sr_module_blwl_pin_id++;
} }
} }
} }

17
openfpga/src/utils/memory_bank_utils.cpp
View File

@ -90,11 +90,10 @@ size_t compute_memory_bank_regional_num_bls(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib, const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model) { const CircuitModelId& sram_model) {
size_t num_bls = 0; size_t num_bls = 0;
std::map<int, size_t> num_bls_per_tile = compute_memory_bank_regional_bitline_numbers_per_tile(module_manager, top_module,
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) { config_region, circuit_lib, sram_model);
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; for (const auto& pair : num_bls_per_tile) {
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id]; num_bls += pair.second;
num_bls += find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_BL);
} }
return num_bls; return num_bls;
@ -123,10 +122,10 @@ size_t compute_memory_bank_regional_num_wls(const ModuleManager& module_manager,
const CircuitModelId& sram_model) { const CircuitModelId& sram_model) {
size_t num_wls = 0; size_t num_wls = 0;
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) { std::map<int, size_t> num_wls_per_tile = compute_memory_bank_regional_wordline_numbers_per_tile(module_manager, top_module,
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; config_region, circuit_lib, sram_model);
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id]; for (const auto& pair : num_wls_per_tile) {
num_wls += find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_WL); num_wls += pair.second;
} }
return num_wls; return num_wls;