diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp
index 206a70728..0c646fa55 100644
--- a/openfpga/src/fabric/build_top_module_memory_bank.cpp
+++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp
@@ -1199,6 +1199,8 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
         ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name);
         BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port);
 
+        cur_sr_module_blwl_pin_id = cur_sr_module_blwl_pin_id % sr_module_blwl_port_info.get_width();
+
         /* Create net */
         ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
                                                        sr_bank_module, sr_bank_instance,
@@ -1210,8 +1212,6 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
         size_t sink_pin_id = sr_banks.shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
         module_manager.add_module_net_sink(top_module, net,
                                            child_module, child_instance, child_blwl_port, sink_pin_id);
-
-        cur_sr_module_blwl_pin_id++;
       }
     }
   }
diff --git a/openfpga/src/utils/memory_bank_utils.cpp b/openfpga/src/utils/memory_bank_utils.cpp
index dcb224fc6..98f0ffca6 100644
--- a/openfpga/src/utils/memory_bank_utils.cpp
+++ b/openfpga/src/utils/memory_bank_utils.cpp
@@ -90,11 +90,10 @@ size_t compute_memory_bank_regional_num_bls(const ModuleManager& module_manager,
                                             const CircuitLibrary& circuit_lib,
                                             const CircuitModelId& sram_model) {
   size_t num_bls = 0;
-
-  for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
-    ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
-    vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id]; 
-    num_bls += find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_BL);
+  std::map<int, size_t> num_bls_per_tile = compute_memory_bank_regional_bitline_numbers_per_tile(module_manager, top_module,
+                                                                                                 config_region, circuit_lib, sram_model);
+  for (const auto& pair : num_bls_per_tile) {
+    num_bls += pair.second;
   }
 
   return num_bls;
@@ -123,10 +122,10 @@ size_t compute_memory_bank_regional_num_wls(const ModuleManager& module_manager,
                                             const CircuitModelId& sram_model) {
   size_t num_wls = 0;
 
-  for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
-    ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
-    vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id]; 
-    num_wls += find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_WL);
+  std::map<int, size_t> num_wls_per_tile = compute_memory_bank_regional_wordline_numbers_per_tile(module_manager, top_module,
+                                                                                                  config_region, circuit_lib, sram_model);
+  for (const auto& pair : num_wls_per_tile) {
+    num_wls += pair.second;
   }
 
   return num_wls;