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[Tool] Remove redundant codes

This commit is contained in:
tangxifan 2021-06-07 21:54:01 -06:00
parent d318b8ebc2
commit 4aef9d5c96
1 changed files with 0 additions and 5 deletions
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5
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -3063,11 +3063,6 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
netlist_annotation, netlist_annotation,
explicit_port_mapping); explicit_port_mapping);
/* Print tasks used for loading bitstreams */
print_verilog_top_testbench_load_bitstream_task(fp,
config_protocol.type(),
module_manager, top_module);
/* load bitstream to FPGA fabric in a configuration phase */ /* load bitstream to FPGA fabric in a configuration phase */
print_verilog_full_testbench_bitstream(fp, print_verilog_full_testbench_bitstream(fp,
bitstream_file, bitstream_file,