From 4aef9d5c9669631b396741370e390659c51dd80c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Jun 2021 21:54:01 -0600 Subject: [PATCH] [Tool] Remove redundant codes --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index c138a3bd9..7d2bc98ef 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -3063,11 +3063,6 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, netlist_annotation, explicit_port_mapping); - /* Print tasks used for loading bitstreams */ - print_verilog_top_testbench_load_bitstream_task(fp, - config_protocol.type(), - module_manager, top_module); - /* load bitstream to FPGA fabric in a configuration phase */ print_verilog_full_testbench_bitstream(fp, bitstream_file,