add fabric bitstream data structure and deploy it to Verilog testbench generation
This commit is contained in:
parent
8c14cced84
commit
4a0e1cd908
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@ -62,6 +62,7 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
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/* Build fabric bitstream here */
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/* Build fabric bitstream here */
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openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
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openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
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openfpga_ctx.module_graph(),
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openfpga_ctx.module_graph(),
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openfpga_ctx.arch().config_protocol,
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cmd_context.option_enable(cmd, opt_verbose));
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cmd_context.option_enable(cmd, opt_verbose));
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/* Write fabric bitstream if required */
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/* Write fabric bitstream if required */
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@ -16,6 +16,7 @@
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#include "netlist_manager.h"
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#include "netlist_manager.h"
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#include "openfpga_flow_manager.h"
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#include "openfpga_flow_manager.h"
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#include "bitstream_manager.h"
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#include "bitstream_manager.h"
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#include "fabric_bitstream.h"
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#include "device_rr_gsb.h"
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#include "device_rr_gsb.h"
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#include "io_location_map.h"
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#include "io_location_map.h"
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@ -61,7 +62,7 @@ class OpenfpgaContext : public Context {
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const openfpga::ModuleManager& module_graph() const { return module_graph_; }
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const openfpga::ModuleManager& module_graph() const { return module_graph_; }
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const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
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const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
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const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
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const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
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const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
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const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; }
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const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
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const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
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const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
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const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
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const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
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const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
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@ -79,7 +80,7 @@ class OpenfpgaContext : public Context {
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openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
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openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
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openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
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openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
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openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
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openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
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std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
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openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; }
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openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
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openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
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std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
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std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
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openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
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openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
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@ -120,7 +121,7 @@ class OpenfpgaContext : public Context {
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/* Bitstream database */
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/* Bitstream database */
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openfpga::BitstreamManager bitstream_manager_;
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openfpga::BitstreamManager bitstream_manager_;
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std::vector<openfpga::ConfigBitId> fabric_bitstream_;
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openfpga::FabricBitstream fabric_bitstream_;
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/* Netlist database
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/* Netlist database
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* TODO: Each format should have an independent entry
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* TODO: Each format should have an independent entry
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@ -28,11 +28,11 @@ namespace openfpga {
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* in the configurable_children) and configurable_child_instances() of each module of module manager
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* in the configurable_children) and configurable_child_instances() of each module of module manager
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*******************************************************************/
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*******************************************************************/
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static
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static
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void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& bitstream_manager,
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const ConfigBlockId& parent_block,
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const ConfigBlockId& parent_block,
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const ModuleManager& module_manager,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& parent_module,
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std::vector<ConfigBitId>& fabric_bitstream) {
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FabricBitstream& fabric_bitstream) {
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/* Depth-first search: if we have any children in the parent_block,
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/* Depth-first search: if we have any children in the parent_block,
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* we dive to the next level first!
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* we dive to the next level first!
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@ -51,7 +51,7 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
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VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
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VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
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/* Go recursively */
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/* Go recursively */
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rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block,
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rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, child_block,
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module_manager, child_module,
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module_manager, child_module,
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fabric_bitstream);
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fabric_bitstream);
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}
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}
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@ -64,45 +64,47 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
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* And then, we can return
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* And then, we can return
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*/
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*/
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for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
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for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
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fabric_bitstream.push_back(config_bit);
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fabric_bitstream.add_bit(config_bit);
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}
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}
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}
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}
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/********************************************************************
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/********************************************************************
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* A top-level function re-organizes the bitstream for a specific
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* Main function to build a fabric-dependent bitstream
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* FPGA fabric, where configuration bits are organized in the sequence
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* by considering the configuration protocol types
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* that can be directly loaded to the FPGA configuration protocol.
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* Support:
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* 1. Configuration chain
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* 2. Memory decoders
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* This function does NOT modify the bitstream database
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* Instead, it builds a vector of ids for configuration bits in bitstream manager
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*
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* This function can be called ONLY after the function build_device_bitstream()
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* Note that this function does NOT decode bitstreams from circuit implementation
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* It was done in the function build_device_bitstream()
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*******************************************************************/
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*******************************************************************/
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std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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static
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void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protocol,
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const BitstreamManager& bitstream_manager,
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const ConfigBlockId& top_block,
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const ModuleManager& module_manager,
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const ModuleManager& module_manager,
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const bool& verbose) {
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const ModuleId& top_module,
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std::vector<ConfigBitId> fabric_bitstream;
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FabricBitstream& fabric_bitstream) {
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vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
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switch (config_protocol.type()) {
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case CONFIG_MEM_STANDALONE: {
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/* Get the top module name in module manager, which is our starting point */
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rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Find the top block in bitstream manager, which has not parents */
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std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
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/* Make sure we have only 1 top block and its name matches the top module */
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VTR_ASSERT(1 == top_block.size());
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VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
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rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0],
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module_manager, top_module,
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module_manager, top_module,
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fabric_bitstream);
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fabric_bitstream);
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break;
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}
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case CONFIG_MEM_SCAN_CHAIN: {
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rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
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module_manager, top_module,
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fabric_bitstream);
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fabric_bitstream.reverse();
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break;
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}
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case CONFIG_MEM_MEMORY_BANK: {
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break;
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}
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case CONFIG_MEM_FRAME_BASED: {
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break;
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}
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid SRAM organization.\n");
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exit(1);
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}
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/* Time-consuming sanity check: Uncomment these codes only for debugging!!!
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/* Time-consuming sanity check: Uncomment these codes only for debugging!!!
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* Check which configuration bits are not touched
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* Check which configuration bits are not touched
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@ -124,11 +126,50 @@ std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager
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*/
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*/
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/* Ensure our fabric bitstream is in the same size as device bistream */
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/* Ensure our fabric bitstream is in the same size as device bistream */
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VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
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VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.bits().size());
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}
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/********************************************************************
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* A top-level function re-organizes the bitstream for a specific
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* FPGA fabric, where configuration bits are organized in the sequence
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* that can be directly loaded to the FPGA configuration protocol.
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* Support:
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* 1. Configuration chain
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* 2. Memory decoders
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* This function does NOT modify the bitstream database
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* Instead, it builds a vector of ids for configuration bits in bitstream manager
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*
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* This function can be called ONLY after the function build_device_bitstream()
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* Note that this function does NOT decode bitstreams from circuit implementation
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* It was done in the function build_device_bitstream()
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*******************************************************************/
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FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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const ModuleManager& module_manager,
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const ConfigProtocol& config_protocol,
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const bool& verbose) {
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FabricBitstream fabric_bitstream;
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vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
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/* Get the top module name in module manager, which is our starting point */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Find the top block in bitstream manager, which has not parents */
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std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
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/* Make sure we have only 1 top block and its name matches the top module */
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VTR_ASSERT(1 == top_block.size());
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VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
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build_module_fabric_dependent_bitstream(config_protocol,
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bitstream_manager, top_block[0],
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module_manager, top_module,
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fabric_bitstream);
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VTR_LOGV(verbose,
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VTR_LOGV(verbose,
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"Built %lu configuration bits for fabric\n",
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"Built %lu configuration bits for fabric\n",
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fabric_bitstream.size());
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fabric_bitstream.bits().size());
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return fabric_bitstream;
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return fabric_bitstream;
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}
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}
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@ -5,7 +5,9 @@
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* Include header files that are required by function declaration
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* Include header files that are required by function declaration
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*******************************************************************/
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*******************************************************************/
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#include <vector>
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#include <vector>
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#include "config_protocol.h"
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#include "bitstream_manager.h"
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#include "bitstream_manager.h"
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#include "fabric_bitstream.h"
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#include "module_manager.h"
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#include "module_manager.h"
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/********************************************************************
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/********************************************************************
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/* begin namespace openfpga */
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/* begin namespace openfpga */
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namespace openfpga {
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namespace openfpga {
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std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
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const ModuleManager& module_manager,
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const ModuleManager& module_manager,
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const ConfigProtocol& config_protocol,
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const bool& verbose);
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const bool& verbose);
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} /* end namespace openfpga */
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} /* end namespace openfpga */
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@ -67,6 +67,12 @@ void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
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bit_dins_[bit_id] = din;
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bit_dins_[bit_id] = din;
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}
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}
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void FabricBitstream::reverse() {
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std::reverse(config_bit_ids_.begin(), config_bit_ids_.end());
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std::reverse(bit_addresses_.begin(), bit_addresses_.end());
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std::reverse(bit_dins_.begin(), bit_dins_.end());
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}
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/******************************************************************************
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/******************************************************************************
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* Public Validators
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* Public Validators
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******************************************************************************/
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******************************************************************************/
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@ -67,6 +67,11 @@ class FabricBitstream {
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void set_bit_din(const FabricBitId& bit_id,
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void set_bit_din(const FabricBitId& bit_id,
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const bool& din);
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const bool& din);
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/* Reverse bit sequence of the fabric bitstream
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* This is required by configuration chain protocol
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*/
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void reverse();
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public: /* Public Validators */
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public: /* Public Validators */
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bool valid_bit_id(const FabricBitId& bit_id) const;
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bool valid_bit_id(const FabricBitId& bit_id) const;
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* in this file
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* in this file
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*******************************************************************/
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*******************************************************************/
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void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
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void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
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const std::vector<ConfigBitId>& fabric_bitstream,
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const FabricBitstream& fabric_bitstream,
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const std::string& fname) {
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const std::string& fname) {
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/* Ensure that we have a valid file name */
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/* Ensure that we have a valid file name */
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if (true == fname.empty()) {
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if (true == fname.empty()) {
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VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
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VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
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}
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}
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std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
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std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.bits().size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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/* Create the file stream */
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@ -48,8 +48,8 @@ void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manag
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check_file_stream(fname.c_str(), fp);
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check_file_stream(fname.c_str(), fp);
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/* Put down pure 0|1 bitstream here */
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/* Put down pure 0|1 bitstream here */
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for (const ConfigBitId& fabric_bit : fabric_bitstream) {
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for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) {
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fp << bitstream_manager.bit_value(fabric_bit);
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fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit));
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}
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}
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/* Print an end to the file here */
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/* Print an end to the file here */
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fp << std::endl;
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fp << std::endl;
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#include <string>
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#include <string>
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#include <vector>
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#include <vector>
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#include "bitstream_manager.h"
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#include "bitstream_manager.h"
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#include "fabric_bitstream.h"
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/********************************************************************
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/********************************************************************
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* Function declaration
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* Function declaration
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namespace openfpga {
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namespace openfpga {
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void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
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void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
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const std::vector<ConfigBitId>& fabric_bitstream,
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const FabricBitstream& fabric_bitstream,
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const std::string& fname);
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const std::string& fname);
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} /* end namespace openfpga */
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} /* end namespace openfpga */
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@ -147,7 +147,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
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********************************************************************/
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********************************************************************/
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void fpga_verilog_testbench(const ModuleManager& module_manager,
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void fpga_verilog_testbench(const ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager,
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const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream,
|
const FabricBitstream& fabric_bitstream,
|
||||||
const AtomContext& atom_ctx,
|
const AtomContext& atom_ctx,
|
||||||
const PlacementContext& place_ctx,
|
const PlacementContext& place_ctx,
|
||||||
const IoLocationMap& io_location_map,
|
const IoLocationMap& io_location_map,
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
#include "netlist_manager.h"
|
#include "netlist_manager.h"
|
||||||
#include "module_manager.h"
|
#include "module_manager.h"
|
||||||
#include "bitstream_manager.h"
|
#include "bitstream_manager.h"
|
||||||
|
#include "fabric_bitstream.h"
|
||||||
#include "simulation_setting.h"
|
#include "simulation_setting.h"
|
||||||
#include "io_location_map.h"
|
#include "io_location_map.h"
|
||||||
#include "vpr_netlist_annotation.h"
|
#include "vpr_netlist_annotation.h"
|
||||||
|
@ -41,7 +42,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
|
||||||
|
|
||||||
void fpga_verilog_testbench(const ModuleManager& module_manager,
|
void fpga_verilog_testbench(const ModuleManager& module_manager,
|
||||||
const BitstreamManager& bitstream_manager,
|
const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream,
|
const FabricBitstream& fabric_bitstream,
|
||||||
const AtomContext& atom_ctx,
|
const AtomContext& atom_ctx,
|
||||||
const PlacementContext& place_ctx,
|
const PlacementContext& place_ctx,
|
||||||
const IoLocationMap& io_location_map,
|
const IoLocationMap& io_location_map,
|
||||||
|
|
|
@ -694,7 +694,7 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp,
|
||||||
static
|
static
|
||||||
void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
|
void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
|
||||||
const BitstreamManager& bitstream_manager,
|
const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream) {
|
const FabricBitstream& fabric_bitstream) {
|
||||||
/* Validate the file stream */
|
/* Validate the file stream */
|
||||||
valid_file_stream(fp);
|
valid_file_stream(fp);
|
||||||
|
|
||||||
|
@ -720,11 +720,9 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
|
||||||
/* Attention: the configuration chain protcol requires the last configuration bit is fed first
|
/* Attention: the configuration chain protcol requires the last configuration bit is fed first
|
||||||
* We will visit the fabric bitstream in a reverse way
|
* We will visit the fabric bitstream in a reverse way
|
||||||
*/
|
*/
|
||||||
std::vector<ConfigBitId> cc_bitstream = fabric_bitstream;
|
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
|
||||||
std::reverse(cc_bitstream.begin(), cc_bitstream.end());
|
|
||||||
for (const ConfigBitId& bit_id : cc_bitstream) {
|
|
||||||
fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME);
|
fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME);
|
||||||
fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl;
|
fp << "(1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)) << ");" << std::endl;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Raise the flag of configuration done when bitstream loading is complete */
|
/* Raise the flag of configuration done when bitstream loading is complete */
|
||||||
|
@ -753,7 +751,7 @@ static
|
||||||
void print_verilog_top_testbench_bitstream(std::fstream& fp,
|
void print_verilog_top_testbench_bitstream(std::fstream& fp,
|
||||||
const e_config_protocol_type& sram_orgz_type,
|
const e_config_protocol_type& sram_orgz_type,
|
||||||
const BitstreamManager& bitstream_manager,
|
const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream) {
|
const FabricBitstream& fabric_bitstream) {
|
||||||
/* Branch on the type of configuration protocol */
|
/* Branch on the type of configuration protocol */
|
||||||
switch (sram_orgz_type) {
|
switch (sram_orgz_type) {
|
||||||
case CONFIG_MEM_STANDALONE:
|
case CONFIG_MEM_STANDALONE:
|
||||||
|
@ -794,7 +792,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
|
||||||
*******************************************************************/
|
*******************************************************************/
|
||||||
void print_verilog_top_testbench(const ModuleManager& module_manager,
|
void print_verilog_top_testbench(const ModuleManager& module_manager,
|
||||||
const BitstreamManager& bitstream_manager,
|
const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream,
|
const FabricBitstream& fabric_bitstream,
|
||||||
const e_config_protocol_type& sram_orgz_type,
|
const e_config_protocol_type& sram_orgz_type,
|
||||||
const CircuitLibrary& circuit_lib,
|
const CircuitLibrary& circuit_lib,
|
||||||
const std::vector<CircuitPortId>& global_ports,
|
const std::vector<CircuitPortId>& global_ports,
|
||||||
|
@ -842,7 +840,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
|
||||||
* by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
|
* by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
|
||||||
* We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
|
* We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
|
||||||
*/
|
*/
|
||||||
size_t num_config_clock_cycles = 1 + fabric_bitstream.size();
|
size_t num_config_clock_cycles = 1 + fabric_bitstream.bits().size();
|
||||||
|
|
||||||
/* Generate stimuli for general control signals */
|
/* Generate stimuli for general control signals */
|
||||||
print_verilog_top_testbench_generic_stimulus(fp,
|
print_verilog_top_testbench_generic_stimulus(fp,
|
||||||
|
|
|
@ -8,6 +8,7 @@
|
||||||
#include <vector>
|
#include <vector>
|
||||||
#include "module_manager.h"
|
#include "module_manager.h"
|
||||||
#include "bitstream_manager.h"
|
#include "bitstream_manager.h"
|
||||||
|
#include "fabric_bitstream.h"
|
||||||
#include "circuit_library.h"
|
#include "circuit_library.h"
|
||||||
#include "vpr_context.h"
|
#include "vpr_context.h"
|
||||||
#include "io_location_map.h"
|
#include "io_location_map.h"
|
||||||
|
@ -23,7 +24,7 @@ namespace openfpga {
|
||||||
|
|
||||||
void print_verilog_top_testbench(const ModuleManager& module_manager,
|
void print_verilog_top_testbench(const ModuleManager& module_manager,
|
||||||
const BitstreamManager& bitstream_manager,
|
const BitstreamManager& bitstream_manager,
|
||||||
const std::vector<ConfigBitId>& fabric_bitstream,
|
const FabricBitstream& fabric_bitstream,
|
||||||
const e_config_protocol_type& sram_orgz_type,
|
const e_config_protocol_type& sram_orgz_type,
|
||||||
const CircuitLibrary& circuit_lib,
|
const CircuitLibrary& circuit_lib,
|
||||||
const std::vector<CircuitPortId>& global_ports,
|
const std::vector<CircuitPortId>& global_ports,
|
||||||
|
|
Loading…
Reference in New Issue