Added fpga_task cmd options in doc [ci skip]
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@ -55,7 +55,8 @@ extensions = [
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'sphinx.ext.todo',
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'sphinx.ext.mathjax',
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'sphinx.ext.graphviz',
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'sphinxcontrib.bibtex'
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'sphinxcontrib.bibtex',
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'sphinx.ext.autosectionlabel',
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]
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# Add any paths that contain templates here, relative to this directory.
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@ -89,7 +90,7 @@ pygments_style = 'sphinx'
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# If true, `todo` and `todoList` produce output, else they produce nothing.
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todo_include_todos = True
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#Number figures for referencing
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# Number figures for referencing
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numfig = True
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@ -114,7 +114,7 @@ General Arguments
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.. option:: --debug
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To enable detail logs printing.
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To enable detailed log printing.
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.. option:: --flow_config
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@ -4,17 +4,17 @@ OpenFPGA Task
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---------------
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Tasks provide a framework for running the :ref:`run_fpga_flow` on
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multiple benchmarks, architectures and set of OpenFPGA parameters.
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multiple benchmarks, architectures, and set of OpenFPGA parameters.
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The structure of the framework is very similar to
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`VTR-Tasks <https://docs.verilogtorouting.org/en/latest/vtr/tasks/>`_
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implementation with additional functionality and minor file extention changes.
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implementation with additional functionality and minor file extension changes.
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Task Directory
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~~~~~~~~~~~~~~
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The tasks are store in a ``TASK_DIRECTORY``, which by default points to
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The tasks are stored in a ``TASK_DIRECTORY``, which by default points to
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``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in
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task directory consisting of ``../config/task.conf`` file can be reffered as a
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task directory consisting of ``../config/task.conf`` file can be referred to as a
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task.
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To create as task name called ``basic_flow`` following directory has to exist::
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@ -31,22 +31,55 @@ Running OpenFPGA Task:
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At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
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open_fpga_flow.py <task1_name> <task2_name> ...
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open_fpga_flow.py <task1_name> <task2_name> ... [<options>]
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where:
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* ``<task_name>`` is the name of the task to run
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* ``<options>`` Other command line arguments described below
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Craeating A New OpenFPGA Task:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Create the folder ``${TASK_DIRECTORY}/<task_name>`` and create a file called
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``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it.
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Command-line Options
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~~~~~~~~~~~~~~~~~~~~
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.. option:: --maxthreads <number_of_threads>
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This option defines the number of threads to run while executing task.
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Each combination of architecture, benchmark and set of OpenFPGA Flow options
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runs in a individual thread.
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.. option:: --skip_thread_logs
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Passsing this option skips printing logs from each OpenFPGA Flow script run.
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.. option:: --exit_on_fail
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Passsing this option exits the OpenFPGA task script with returncode 1,
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if any threads fail to execute successfully. It is mainly used to while
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performing regression test.
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.. option:: --test_run
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This option allows to debug OpenFPGA Task script
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by skiping actual execution of OpenFPGA flow .
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Passing this option prints the list of
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commnad generated to execute using OpenFPGA flow.
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.. option:: --debug
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To enable detailed log printing.
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Creating a new OpenFPGA Task
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Configuring a New Task
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~~~~~~~~~~~~~~~~~~~~~~
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- Create the folder ``${TASK_DIRECTORY}/<task_name>``
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- Create a file ``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it
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- Configure the task as explained in :ref:`Configuring a new OpenFPGA Task`
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Configuring a new OpenFPGA Task
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The task configuration file ``task.conf`` consists of ``GENERAL``,
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``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and
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@ -54,16 +87,16 @@ The task configuration file ``task.conf`` consists of ``GENERAL``,
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Declaring all the above sections are mandatory.
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.. note::
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Configuration file supports all the OpenFPGA Variables refer
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:ref:`openfpga-variables` section to know more. Variables in configuration
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file is declares as ``${PATH:<variable_name>}``
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The configuration file supports all the OpenFPGA Variables refer
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:ref:`openfpga-variables` section to know more. Variable in the configuration
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file is declared as ``${PATH:<variable_name>}``
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General Section
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^^^^^^^^^^^^^^^
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.. option:: fpga_flow==<yosys_vpr|vpr_blif>
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Defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
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This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
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.. option:: power_analysis=<true|false>
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@ -71,7 +104,7 @@ General Section
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.. option:: power_tech_file=<path_to_tech_XML_file>
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Declares which tech XML file to be used while perforing Power Analysis.
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Declares which tech XML file to use while performing Power Analysis.
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.. option:: spice_output=<true|false>
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@ -85,14 +118,13 @@ General Section
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.. option:: timeout_each_job=<true|false>
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Specifies the the timeout for each :ref:`run_fpga_flow` execution. Default
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is set to ``20 min``
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Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. ``
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Architectures Sections
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^^^^^^^^^^^^^^^^^^^^^^
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User can define the list of architecure files in this section.
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User can define the list of architecture files in this section.
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.. option:: arch<arch_label>=<xml_architecture_file_path>
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@ -102,7 +134,7 @@ Architectures Sections
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.. note::
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In final OpenFPGA Task result the architecture will be referred by its
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In the final OpenFPGA Task result, the architecture will be referred by its
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``arch_label``.
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Benchmarks Sections
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@ -117,7 +149,7 @@ Benchmarks Sections
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architecture file
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For Example following code shows how to define a benchmarks,
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with single file multiple files and files added from specific directory.
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with a single file, multiple files and files added from a specific directory.
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.. code-block:: text
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@ -133,17 +165,17 @@ Benchmarks Sections
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.. note::
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``bench_label`` is referred again in ``Synthesis_Param`` section to
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provide addional information about benchmark
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provide additional information about benchmark
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Synthesis Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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User can define extra parameters for each benchmark defined in the
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User can define extra parameters for each benchmark in the
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``BENCHMARKS`` sections.
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.. option:: bench<bench_label>_top=<Top_Module_Name>
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This defines the Top Level module name for ``bench_label`` benchmark.
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By default, the top level module name is cosidereed as a ``top``.
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This option defines the Top Level module name for ``bench_label`` benchmark.
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By default, the top-level module name is considered as a ``top``.
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.. option:: bench<bench_label>_yosys_tmpl=<yosys_template_file>
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@ -163,13 +195,13 @@ Synthesis Parameter Sections
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.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
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In case of running ``blif_vpr_flow`` with verification this option provides
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the source verilog design for ``bench_label`` benchmark to be used
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the source Verilog design for ``bench_label`` benchmark to be used
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while verification.
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Script Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
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The section is referred with ``parameter_set_label`` in final result file.
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The section is referred with ``parameter_set_label`` in the final result file.
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For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments.
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@ -184,7 +216,7 @@ For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fi
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fix_route_chan_width=50
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Example Task Configuration File
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block:: text
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[GENERAL]
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@ -210,4 +242,3 @@ Example Task Configuration File
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[SCRIPT_PARAM_Slack_80]
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min_route_chan_width=1.8
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@ -55,7 +55,7 @@ parser.add_argument('--debug', action="store_true",
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help="Run script in debug mode")
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parser.add_argument('--exit_on_fail', action="store_true",
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help="Exit script with return code")
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parser.add_argument('--skip_tread_logs', action="store_true",
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parser.add_argument('--skip_thread_logs', action="store_true",
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help="Skips logs from running thread")
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args = parser.parse_args()
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@ -364,7 +364,7 @@ def run_single_script(s, eachJob):
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stderr=subprocess.STDOUT,
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universal_newlines=True)
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for line in process.stdout:
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if not args.skip_tread_logs:
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if not args.skip_thread_logs:
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strip_child_logger_info(line[:-1])
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sys.stdout.buffer.flush()
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output.write(line)
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