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adapt benchmark and_latch module name to be different than benchmark and

This commit is contained in:
tangxifan 2020-04-20 13:15:05 -06:00
parent f6b7583a2a
commit 489ca75230
4 changed files with 5 additions and 5 deletions
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4
openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
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@ -1,5 +1,5 @@
# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
.model top
# Benchmark "and_latch" written by ABC on Wed Mar 11 10:36:28 2020
.model and_latch
.inputs a b clk
.outputs c d

2
openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
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@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module top(
module and_latch(
a,
b,
clk,

2
openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
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@ -30,7 +30,7 @@ bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
bench1_top = top
bench1_top = and_latch
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v

2
openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
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@ -29,7 +29,7 @@ bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
bench1_top = top
bench1_top = and_latch
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v