diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
index dbd863d9c..0a064691b 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
@@ -1,5 +1,5 @@
-# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
-.model top
+# Benchmark "and_latch" written by ABC on Wed Mar 11 10:36:28 2020
+.model and_latch
 .inputs a b clk
 .outputs c d
 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
index a8f147f5b..b874d558c 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module top(
+module and_latch(
   a,
   b,
   clk,
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index 76c70bb6c..d1d9ba17e 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -30,7 +30,7 @@ bench0_top = top
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 
-bench1_top = top
+bench1_top = and_latch
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
 
diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
index 566b7e353..714874d13 100644
--- a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
@@ -29,7 +29,7 @@ bench0_top = top
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 
-bench1_top = top
+bench1_top = and_latch
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v