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Merge pull request #824 from lnis-uofu/place_rr_graph 

Fix a bug where placer does not call tileable rr-graph generator
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tangxifan 2022-10-04 12:08:56 -07:00 committed by GitHub
parent b652bc8d51 ab53f88c2b
commit 46044d5217
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3 changed files with 12 additions and 3 deletions
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3
openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
View File

@ -16,9 +16,10 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif fpga_flow=vpr_blif
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml

8
openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
View File

@ -69,6 +69,14 @@
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="6" height="6">
<!-- Perimeter of 'EMPTY' blocks -->
<perimeter type="EMPTY" priority="100"/>
<!--Fill with 'io'-->
<fill type="io" priority="10"/>
<!-- Build an inner region of clbs -->
<region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/>
</fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 942d1bbfff837d9c5409f6f0932dec574fb7e7c2 Subproject commit 5226096ee94b2b589078926a203fe71996343992