diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
index 3c2aa65cc..989f8e09a 100644
--- a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
diff --git a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
index a8f9bfded..9fb3b8057 100644
--- a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
@@ -69,6 +69,14 @@
          <!--Fill with 'clb'-->   
          <fill type="clb" priority="10"/>   
       </auto_layout>  
+      <fixed_layout name="2x2" width="6" height="6">   
+         <!-- Perimeter of 'EMPTY' blocks -->   
+         <perimeter type="EMPTY" priority="100"/>   
+         <!--Fill with 'io'-->   
+         <fill type="io" priority="10"/>   
+         <!-- Build an inner region of clbs -->   
+         <region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/>    
+      </fixed_layout>  
    </layout> 
    <device>  
       <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
@@ -293,4 +301,4 @@
       </pb_type>  
       <!-- Define general purpose logic block (CLB) ends -->  
    </complexblocklist> 
-</architecture>
\ No newline at end of file
+</architecture>
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index 942d1bbff..5226096ee 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit 942d1bbfff837d9c5409f6f0932dec574fb7e7c2
+Subproject commit 5226096ee94b2b589078926a203fe71996343992