single mode is working, multi-mode is under debugging

openfpga_flow/VerilogNetlists/ff.v

@@ -76,9 +76,9 @@ endmodule //End Of Module static_dff
 //-----------------------------------------------------
 module sc_dff_compact (
 /* Global ports go first */
-input reset, // Reset input
+input pReset, // Reset input
 //input set,     // set input
-input clk, // Clock Input
+input prog_clk, // Clock Input
 /* Local ports follow */
 input D, // Data Input
 output Q, // Q output
@@ -88,8 +88,8 @@ output Qb // Q output
 reg q_reg;
 
 //-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset /*or posedge set*/)
+always @ ( posedge prog_clk or posedge pReset /*or posedge set*/)
-if (reset) begin
+if (pReset) begin
   q_reg <= 1'b0;
 //end else if (set) begin
 //  q_reg <= 1'b1;

openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml

@@ -321,12 +321,12 @@
         <input_buffer exist="on" circuit_model_name="INV1X"/>
         <output_buffer exist="on" circuit_model_name="INV1X"/>
         <pass_gate_logic circuit_model_name="TGATEX1"/>
-        <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+        <port type="input" prefix="pReset" lib_name="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
         <!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
-        <port type="input" prefix="D" size="1"/>
+        <port type="input" prefix="D" lib_name="D" size="1"/>
-        <port type="output" prefix="Q" size="1"/>
+        <port type="output" prefix="Q" lib_name="Q" size="1"/>
-        <port type="output" prefix="Qb" size="1"/>
+        <port type="output" prefix="Qb" lib_name="Qb" size="1"/>
-        <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+        <port type="clock" prefix="prog_clk" lib_name="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
       </circuit_model>
       <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
         <design_technology type="cmos"/>

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp

@@ -112,7 +112,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb,
   /* TOP side I/Os */
   if (device_size.y() - 1 == y) {
     io_index = io_index_offset[io_side];
-    for (size_t ix = 1; ix < x - 1; ++ix) {
+    for (size_t ix = 1; ix < x ; ++ix) {
       io_index += L_grids[ix][y].type->capacity; 
     }
     io_index += z;
@@ -120,7 +120,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb,
   /* RIGHT side I/Os */
   if (device_size.x() - 1 == x) {
     io_index = io_index_offset[io_side];
-    for (size_t iy = 1; iy < y - 1; ++iy) {
+    for (size_t iy = 1; iy < y; ++iy) {
       io_index += L_grids[x][iy].type->capacity; 
     }
     io_index += z;
@@ -128,7 +128,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb,
   /* BOTTOM side I/Os */
   if (0 == y) {
     io_index = io_index_offset[io_side];
-    for (size_t ix = 1; ix < x - 1; ++ix) {
+    for (size_t ix = 1; ix < x; ++ix) {
       io_index += L_grids[ix][y].type->capacity; 
     }
     io_index += z;
@@ -136,7 +136,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb,
   /* LEFT side I/Os */
   if (0 == x) {
     io_index = io_index_offset[io_side];
-    for (size_t iy = 1; iy < y - 1; ++iy) {
+    for (size_t iy = 1; iy < y; ++iy) {
       io_index += L_grids[x][iy].type->capacity; 
     }
     io_index += z;

vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp

@@ -35,7 +35,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
 
   /* Add ports */
   /* Find global ports and add one by one */
-  for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) {
+  for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
     BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
     module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
   }
@@ -163,10 +163,41 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
   size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); 
 
   /* Add ports to the module manager */
-  for (const std::string& sram_port_name : sram_port_names) {
+  switch (sram_orgz_type) {
-    /* Add generated ports to the ModuleManager */
+  case SPICE_SRAM_STANDALONE: 
-    BasicPort sram_port(sram_port_name, sram_port_size);
+  case SPICE_SRAM_MEMORY_BANK: {
-    module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+    }
+    break;
+  }
+  case SPICE_SRAM_SCAN_CHAIN: { 
+    /* Note that configuration chain tail is an output while head is an input 
+     * IMPORTANT: this is co-designed with function generate_sram_port_names()
+     * If the return vector is changed, the following codes MUST be adapted!
+     */
+    VTR_ASSERT(2 == sram_port_names.size());
+    size_t port_counter = 0;
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      if (0 == port_counter) { 
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+      } else {
+        VTR_ASSERT(1 == port_counter);
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_OUTPUT_PORT);
+      }
+      port_counter++;
+    }
+    break;
+  }
+  default:
+    vpr_printf(TIO_MESSAGE_ERROR,
+               "(File:%s,[LINE%d]) Invalid type of SRAM organization !\n",
+               __FILE__, __LINE__);
+    exit(1);
   }
 }
 
@@ -457,7 +488,7 @@ void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_m
     for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) {
       ModuleNetId net = module_manager.create_module_net(parent_module);
       /* TODO: Give a name to make it clear */
-      std::string net_name = module_manager.module_name(logic_module) + std::string("_") + logic_module_sram_ports[port_index].get_name();
+      std::string net_name = module_manager.module_name(logic_module) + std::string("_") + std::to_string(logic_instance_id) + std::string("_") + logic_module_sram_ports[port_index].get_name();
       module_manager.set_net_name(parent_module, net, net_name);
       /* Add net source */
       module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]);

vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp

@@ -183,10 +183,10 @@ std::string generate_mask_bits(const size_t& mask_code,
   for (const size_t& mask_bit : mask_bits) {
     VTR_ASSERT( 0 == mask_bit || 1 == mask_bit );
     if (0 == mask_bit) {
-      mask_bits_str.push_back('1');
+      mask_bits_str.push_back('0');
       continue;
     }
-    mask_bits_str.push_back('0');
+    mask_bits_str.push_back('1');
   }
  
   return mask_bits_str;
@@ -496,6 +496,10 @@ std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
     /* Find the corresponding circuit model output port and assoicated lut_output_mask */
     CircuitPortId lut_model_output_port = lut_pb->lut_output_pb_graph_pin[ilb]->port->circuit_model_port;
     size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
+    /* By default, lut_frac_level will be the lut_size, i.e., number of levels of the mux graph */
+    if ( size_t(-1) == lut_frac_level ) {
+      lut_frac_level = lut_mux_graph.num_levels();
+    }
 
     /* Find the corresponding circuit model output port and assoicated lut_output_mask */
     size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_pb->lut_output_pb_graph_pin[ilb]->pin_number];

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp

@@ -286,24 +286,6 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Ensure that the module has been created and thus unique! */
   VTR_ASSERT(ModuleId::INVALID() != primitive_module);
 
-  /* Find the global ports required by the primitive node, and add them to the module */
-  std::vector<CircuitPortId> primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true);
-  for (auto port : primitive_model_global_ports) {
-    /* The global I/O of the FPGA has a special name */
-    BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
-    module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT);
-  }
-
-  /* Find the inout ports required by the primitive node, and add them to the module
-   * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric
-   */
-  if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
-    std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT);
-    for (auto port : primitive_model_inout_ports) {
-      BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port));
-      module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT);
-    }
-  }
   /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here.
    * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P,
    * no ports of the circuit model will be missing here  
@@ -372,6 +354,33 @@ void build_primitive_block_module(ModuleManager& module_manager,
     add_module_nets_memory_config_bus(module_manager, primitive_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, primitive_module);
+
+  /* Find the inout ports required by the primitive node, and add them to the module
+   * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric
+   */
+  if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
+    std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT);
+    for (auto port : primitive_model_inout_ports) {
+      BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port));
+      ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT);
+      ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_lib_name(port));
+      BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id);
+      VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width());
+
+      /* Wire the GPIO port form primitive_module to the logic module!*/
+      for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
+        ModuleNetId net = module_manager.create_module_net(primitive_module);
+        module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]);
+        module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]);
+      }
+    }
+  }
 }
 
 /********************************************************************

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp

@@ -363,7 +363,7 @@ void build_memory_chain_module(ModuleManager& module_manager,
    */
   BasicPort chain_tail_port(generate_configuration_chain_tail_name(), 
                             circuit_lib.port_size(sram_output_ports[0]));
-  module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_INPUT_PORT);
+  module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
 
   /* Add each output port: port width should match the number of memories */
   for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp

@@ -282,14 +282,16 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
   VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
   BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
   ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); 
+  BasicPort sb_output_port = module_manager.module_port(sb_module, sb_output_port_id);
 
   /* Check port size should match */
-  VTR_ASSERT(1 == mux_output_port.get_width());
+  VTR_ASSERT(sb_output_port.get_width() == mux_output_port.get_width());
   for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) {
     ModuleNetId net = module_manager.create_module_net(sb_module);
-    /* Skip Configuring the net source, it is done before */
+    /* Configuring the net source */
+    module_manager.add_module_net_source(sb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
     /* Configure the net sink */
-    module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, 0);
+    module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, sb_output_port.pins()[pin_id]);
   }
 
   /* Instanciate memory modules */
@@ -754,14 +756,16 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
   VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
   BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
   ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, cur_rr_node);
+  BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id);
 
   /* Check port size should match */
-  VTR_ASSERT(1 == mux_output_port.get_width());
+  VTR_ASSERT(cb_output_port.get_width() == mux_output_port.get_width());
   for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) {
     ModuleNetId net = module_manager.create_module_net(cb_module);
-    /* Skip Configuring the net source, it is done before */
+    /* Configuring the net source */
+    module_manager.add_module_net_source(cb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
     /* Configure the net sink */
-    module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, 0);
+    module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, cb_output_port.pins()[pin_id]);
   }
 
   /* Instanciate memory modules */
@@ -932,7 +936,7 @@ void build_connection_block_module(ModuleManager& module_manager,
   /* Create a cache (fast look up) for module nets whose source are input ports */
   std::map<ModulePortId, ModuleNetId> input_port_to_module_nets;
 
-  /* TODO: Generate short-wire connection for each routing track : 
+  /* Generate short-wire connection for each routing track : 
    * Each input port is short-wired to its output port and middle output port
    *    
    *   in[i] ----------> out[i]
@@ -971,7 +975,7 @@ void build_connection_block_module(ModuleManager& module_manager,
     }
   }
 
-  /* TODO: Add sub modules of routing multiplexers or direct interconnect*/
+  /* Add sub modules of routing multiplexers or direct interconnect*/
   for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
     enum e_side cb_ipin_side = cb_ipin_sides[iside];
     for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp

@@ -79,10 +79,18 @@ DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb,
   }
  
   VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side));
-  DeviceCoordinator side_coord = rr_gsb.get_side_block_coordinator(sb_side);
 
-  gsb_coordinate.set_x(side_coord.get_x()); 
+  /* RIGHT side: x + 1 */
-  gsb_coordinate.set_y(side_coord.get_y()); 
+  if (RIGHT == sb_side) {
+    gsb_coordinate.set_x(rr_gsb.get_x() + 1); 
+    gsb_coordinate.set_y(rr_gsb.get_y()); 
+  }
+
+  /* BOTTOM side: y - 1 */
+  if (BOTTOM == sb_side) {
+    gsb_coordinate.set_x(rr_gsb.get_x()); 
+    gsb_coordinate.set_y(rr_gsb.get_y() - 1); 
+  }
 
   return gsb_coordinate;
 }
@@ -669,10 +677,25 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
     DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side());
     DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side());
 
-    /* Skip those Connection blocks that do not exist */
+    /* Skip those Connection blocks that do not exist:
-    if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
+     * 1. The CB does not exist in the device level! We should skip! 
-      || (true != rr_gsb.is_cb_exist(cb_type))) {
+     * 2. The CB does exist but we need to make sure if the GSB includes such CBs 
-      continue;
+     *    For TOP and LEFT side, check the existence using RRGSB method is_cb_exist()
+     *    FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist()
+     */
+    if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) {
+      if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) 
+        || (true != rr_gsb.is_cb_exist(cb_type))) {
+        continue;
+      }
+    }
+
+    if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) {
+      const RRGSB& adjancent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
+      if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) 
+        || (true != adjancent_gsb.is_cb_exist(cb_type))) {
+        continue;
+      }
     }
 
     /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -408,12 +408,12 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
                                                           + std::string(formal_verification_verilog_file_postfix);
     /* TODO: this is an old function, to be shadowed */
     dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, 
-                                                 formal_verification_top_netlist_file_path.c_str(), src_dir_path);
+                                                 std::string(formal_verification_top_netlist_file_path + std::string(".bak")).c_str(), src_dir_path);
     /* TODO: new function: to be tested */
     print_verilog_preconfig_top_module(module_manager, bitstream_manager, fabric_bitstream, 
                                        Arch.spice->circuit_lib, global_ports, L_logical_blocks,
                                        device_size, L_grids, L_blocks, 
-                                       std::string(chomped_circuit_name), formal_verification_top_netlist_file_path + std::string(".bak"),
+                                       std::string(chomped_circuit_name), formal_verification_top_netlist_file_path,
                                        std::string(src_dir_path)); 
                                        
     /* Output script for formality */

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp

@@ -200,7 +200,7 @@ void print_verilog_grid(ModuleManager& module_manager,
                                                              std::string(verilog_netlist_file_postfix))
                            );
   /* TODO: remove the bak file when the file is ready */
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   /* Echo status */
   if (IO_TYPE == phy_block_type) {
@@ -313,7 +313,7 @@ void print_verilog_grids(ModuleManager& module_manager,
   vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n");
   std::string grid_verilog_fname(logic_block_verilog_file_name);
   /* TODO: remove .bak when it is ready */
-  grid_verilog_fname += ".bak";
+  //grid_verilog_fname += ".bak";
   dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head,
                                   subckt_dir.c_str(),
                                   grid_verilog_fname.c_str());

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c

@@ -23,6 +23,7 @@
 #include "linkedlist.h"
 #include "fpga_x2p_utils.h"
 #include "fpga_x2p_globals.h"
+#include "fpga_x2p_naming.h"
 
 /* Include verilog utils */
 #include "verilog_global.h"
@@ -82,10 +83,13 @@ void write_include_netlists (char* src_dir_formatted,
 	verilog_include_defines_preproc_file(fp, src_dir_formatted);
 	verilog_include_simulation_defines_file(fp, src_dir_formatted);
 
-
+    /*
 	fprintf(fp, "`include \"%s%s%s\"\n",  src_dir_formatted, 
 							chomped_circuit_name, 
 							verilog_top_postfix);
+     */
+	fprintf(fp, "`include \"%s%s\"\n",  src_dir_formatted, 
+							 generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)).c_str());
 	fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
 	fprintf(fp, "`include \"%s%s%s\"\n",  src_dir_formatted, 
 							chomped_circuit_name, 
@@ -95,8 +99,8 @@ void write_include_netlists (char* src_dir_formatted,
 							chomped_circuit_name, 
 							random_top_testbench_verilog_file_postfix);
 	fprintf(fp, "  `endif\n");
-    /* TODO: bring these testbench onboard when it is ready
 	fprintf(fp, "`elsif %s\n", initial_simulation_flag);
+    /* TODO: bring these testbench onboard when it is ready
 	fprintf(fp, "`include \"%s%s%s\"\n",  src_dir_formatted, 
 							chomped_circuit_name, 
 							top_testbench_verilog_file_postfix);
@@ -104,8 +108,8 @@ void write_include_netlists (char* src_dir_formatted,
 	fprintf(fp, "`include \"%s%s%s\"\n",  src_dir_formatted, 
 							chomped_circuit_name, 
 							autocheck_top_testbench_verilog_file_postfix);
-	fprintf(fp, "`endif\n");
     */
+	fprintf(fp, "`endif\n");
 	fprintf(fp, "`include \"%s%s%s\"\n",  src_dir_formatted, 
 							default_rr_dir_name, 
 							routing_verilog_file_name);

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp

@@ -34,7 +34,8 @@ void print_verilog_submodule_luts(ModuleManager& module_manager,
                                   const std::string& submodule_dir,
                                   const bool& use_explicit_port_map) {
   /* TODO: remove .bak when this part is completed and tested */
-  std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak";
+  std::string verilog_fname = submodule_dir + luts_verilog_file_name;
+  //verilog_fname +=".bak";
 
   std::fstream fp;
 

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp

@@ -104,7 +104,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager,
                                       const bool& use_explicit_port_map) {
   /* Plug in with the mux subckt */
   std::string verilog_fname(submodule_dir + memories_verilog_file_name);
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   /* Create the file stream */
   std::fstream fp;

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp

@@ -1217,7 +1217,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
 
   /* TODO: Generate modules into a .bak file now. Rename after it is verified */
   std::string verilog_fname(submodule_dir + muxes_verilog_file_name);
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   /* Create the file stream */
   std::fstream fp;

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp

@@ -80,25 +80,10 @@ void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp,
   check_file_handler(fp);
 
   /* Global ports of top-level module  */
-  print_verilog_comment(fp, std::string("----- Global ports of FPGA fabric -----"));
+  print_verilog_comment(fp, std::string("----- Local wires for FPGA fabric -----"));
-  for (const BasicPort& global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
+  for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) {
-    fp << generate_verilog_port(VERILOG_PORT_WIRE, global_port) << ";" << std::endl;
+    BasicPort module_port = module_manager.module_port(top_module, module_port_id);
-  }
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
-  /* Add an empty line as a splitter */
-  fp << std::endl;
-
-  /* Datapath I/Os of FPGA fabric */
-  print_verilog_comment(fp, std::string("----- I/Os of FPGA fabric -----"));
-  for (const BasicPort& gpio_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) {
-    fp << generate_verilog_port(VERILOG_PORT_WIRE, gpio_port) << ";" << std::endl;
-  }
-  /* Add an empty line as a splitter */
-  fp << std::endl;
-
-  /* Datapath I/Os of FPGA fabric */
-  print_verilog_comment(fp, std::string("----- Configuration protocols of FPGA fabric -----"));
-  for (const BasicPort& input_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_INPUT_PORT)) {
-    fp << generate_verilog_port(VERILOG_PORT_WIRE, input_port) << ";" << std::endl;
   }
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -244,7 +229,12 @@ void print_verilog_preconfig_top_module_connect_ios(std::fstream& fp,
     BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ std::string(formal_verification_top_module_port_postfix)), 1); 
 
     print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
-    print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
+    if (VPACK_INPAD == io_lb.type) {
+      print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
+    } else {
+      VTR_ASSERT(VPACK_OUTPAD == io_lb.type);
+      print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
+    }
 
     /* Mark this I/O has been used/wired */
     io_used[io_index] = true;

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c

@@ -2101,7 +2101,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
   fclose(fp);
 
   /* Add fname to the linked list */
+  /*
   routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname);  
+   */
 
   /* Free chan_rr_nodes */
   my_free(fname);
@@ -2302,7 +2304,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
   fclose(fp);
 
   /* Add fname to the linked list */
+  /*
   routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname);  
+   */
 
   /* Free chan_rr_nodes */
   my_free(fname);
@@ -3368,7 +3372,9 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
   fclose(fp);
 
   /* Add fname to the linked list */
+  /*
   routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname);  
+   */
 
   /* Free */
   my_free(fname);
@@ -3606,7 +3612,9 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
   fclose(fp);
 
   /* Add fname to the linked list */
+  /*
   routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname);  
+   */
 
   /* Free */
   my_free(fname);
@@ -3826,10 +3834,12 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
   }
 
   /* Output a header file for all the routing blocks */
+  /*
   vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
   dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
                                   subckt_dir,
                                   routing_verilog_file_name);
+   */
   
   return;
 }
@@ -3900,7 +3910,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
   std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
   /* TODO: remove the bak file when the file is ready */
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   /* Create the file stream */
   std::fstream fp;
@@ -3927,9 +3937,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma
   fp.close();
 
   /* Add fname to the linked list */
-  /*
+  routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());  
-  routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname);  
-   */
 }
 
 /*********************************************************************
@@ -4005,7 +4013,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
   std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
   /* TODO: remove the bak file when the file is ready */
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   /* Create the file stream */
   std::fstream fp;
@@ -4029,9 +4037,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
   fp.close();
 
   /* Add fname to the linked list */
-  /*
   routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());  
-   */
 
   return;
 }
@@ -4108,6 +4114,10 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
 
   print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
 
+  vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
+  dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
+                                  subckt_dir.c_str(),
+                                  routing_verilog_file_name);
 }
 
 
@@ -4161,4 +4171,10 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager,
                                                        unique_mirror, CHANY,  
                                                        use_explicit_port_map);
   }
+
+  vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
+  dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
+                                  subckt_dir.c_str(),
+                                  routing_verilog_file_name);
+
 }

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp

@@ -42,7 +42,7 @@ void print_verilog_top_module(ModuleManager& module_manager,
   /* Create the file name for Verilog netlist */
   std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)));
   /* TODO: remove the bak file when the file is ready */
-  verilog_fname += ".bak";
+  //verilog_fname += ".bak";
 
   vpr_printf(TIO_MESSAGE_INFO,
              "Writing Verilog Netlist for top-level module of FPGA fabric (%s)...\n",

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp

@@ -173,7 +173,7 @@ void print_verilog_module_ports(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT;
-  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT;
   port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT;
@@ -329,6 +329,7 @@ void print_verilog_module_instance(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT;