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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability

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tangxifan 2022-09-19 21:55:15 -07:00
parent d9bd0a6cf3
commit 40663f956c
1 changed files with 1 additions and 1 deletions
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openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
# VPR parameters # VPR parameters
# # Use a fixed routing channel width to save runtime # # Use a fixed routing channel width to save runtime
vpr_route_chan_width=50 vpr_route_chan_width=60
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml