From 40663f956ca74bceb7d9327a872a5ef61b3df61c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 21:55:15 -0700 Subject: [PATCH] [test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability --- openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf index d1d2d411e..2a4b39517 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # VPR parameters # # Use a fixed routing channel width to save runtime -vpr_route_chan_width=50 +vpr_route_chan_width=60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml