remove dead codes for essential gates code generation
This commit is contained in:
tangxifan
parent
43de2d7636
commit
3f45e6cc87
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@ -132,544 +132,6 @@ void dump_verilog_submodule_signal_init(FILE* fp,
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return;
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}
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/* Dump a module of inverter or buffer or tapered buffer */
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static
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void dump_verilog_invbuf_module(FILE* fp,
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t_spice_model* invbuf_spice_model) {
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int ipin, iport, port_cnt;
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int num_input_port = 0;
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int num_output_port = 0;
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int num_powergate_port = 0;
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t_spice_model_port** input_port = NULL;
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t_spice_model_port** output_port = NULL;
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t_spice_model_port** powergate_port = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n",
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__FILE__, __LINE__);
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exit(1);
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}
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fprintf(fp, "//----- Verilog module for %s -----\n",
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invbuf_spice_model->name);
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/* Find the input port, output port*/
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input_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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powergate_port = find_spice_model_config_done_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_powergate_port, FALSE);
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/* Make sure:
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* There is only 1 input port and 1 output port,
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* each size of which is 1
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*/
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assert(1 == num_input_port);
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assert(1 == input_port[0]->size);
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assert(1 == num_output_port);
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assert(1 == output_port[0]->size);
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/* If power-gated, we need to find enable signals */
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if (TRUE == invbuf_spice_model->design_tech_info.power_gated) {
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if (0 == num_powergate_port) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Inverter, buffer SPICE model is power-gated, but cannot find any power-gate port!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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assert ( 0 < num_powergate_port);
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}
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/* dump module body */
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fprintf(fp, "module %s (\n",
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invbuf_spice_model->name);
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, invbuf_spice_model, TRUE, FALSE, FALSE)) {
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fprintf(fp, ",\n");
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}
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/* Dump ports */
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fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name);
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fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name);
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fprintf(fp, ");\n");
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/* Finish dumping ports */
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/* Assign logics : depending on topology */
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switch (invbuf_spice_model->design_tech_info.buffer_info->type) {
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case SPICE_MODEL_BUF_INV:
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if (TRUE == invbuf_spice_model->design_tech_info.power_gated) {
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/* Create a sensitive list */
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fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name);
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fprintf(fp, "always @(");
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/* Power-gate port first*/
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for (iport = 0; iport < num_powergate_port; iport++) {
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fprintf(fp, "%s,", powergate_port[iport]->lib_name);
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}
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fprintf(fp, "%s) begin\n",
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input_port[0]->lib_name);
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/* Dump the case of power-gated */
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fprintf(fp, " if (");
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port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */
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for (iport = 0; iport < num_powergate_port; iport++) {
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if (0 == powergate_port[iport]->default_val) {
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for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) {
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if ( 0 < port_cnt ) {
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fprintf(fp, "\n\t&&");
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}
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/* Power-gated signal are disable during operating, enabled during configuration,
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* Therefore, we need to reverse them here
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*/
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fprintf(fp, "(~%s[%d])",
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powergate_port[iport]->lib_name,
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ipin);
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port_cnt++; /* Update port counter*/
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}
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} else {
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assert (1 == powergate_port[iport]->default_val);
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for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) {
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if ( 0 < port_cnt ) {
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fprintf(fp, "\n\t&&");
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}
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/* Power-gated signal are disable during operating, enabled during configuration,
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* Therefore, we need to reverse them here
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*/
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fprintf(fp, "(%s[%d])",
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powergate_port[iport]->lib_name,
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ipin);
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port_cnt++; /* Update port counter*/
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}
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}
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}
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fprintf(fp, ") begin\n");
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fprintf(fp, "\t\tassign %s_reg = ~%s;\n",
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output_port[0]->lib_name,
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input_port[0]->lib_name);
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fprintf(fp, "\tend else begin\n");
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fprintf(fp, "\t\tassign %s_reg = 1'bz;\n",
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output_port[0]->lib_name);
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fprintf(fp, "\tend\n");
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fprintf(fp, "end\n");
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fprintf(fp, "assign %s = %s_reg;\n",
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output_port[0]->lib_name,
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output_port[0]->lib_name);
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} else {
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fprintf(fp, "assign %s = (%s === 1'bz)? $random : ~%s;\n",
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output_port[0]->lib_name,
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input_port[0]->lib_name,
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input_port[0]->lib_name);
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}
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break;
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case SPICE_MODEL_BUF_BUF:
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if (TRUE == invbuf_spice_model->design_tech_info.power_gated) {
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/* Create a sensitive list */
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fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name);
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fprintf(fp, "always @(");
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/* Power-gate port first*/
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for (iport = 0; iport < num_powergate_port; iport++) {
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fprintf(fp, "%s,", powergate_port[iport]->lib_name);
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}
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fprintf(fp, "%s) begin\n",
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input_port[0]->lib_name);
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/* Dump the case of power-gated */
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fprintf(fp, " if (");
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port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */
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for (iport = 0; iport < num_powergate_port; iport++) {
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if (0 == powergate_port[iport]->default_val) {
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for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) {
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if ( 0 < port_cnt ) {
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fprintf(fp, "\n\t&&");
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}
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/* Power-gated signal are disable during operating, enabled during configuration,
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* Therefore, we need to reverse them here
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*/
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fprintf(fp, "(~%s[%d])",
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powergate_port[iport]->lib_name,
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ipin);
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port_cnt++; /* Update port counter*/
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}
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} else {
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assert (1 == powergate_port[iport]->default_val);
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for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) {
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if ( 0 < port_cnt ) {
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fprintf(fp, "\n\t&&");
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}
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/* Power-gated signal are disable during operating, enabled during configuration,
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* Therefore, we need to reverse them here
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*/
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fprintf(fp, "(%s[%d])",
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powergate_port[iport]->lib_name,
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ipin);
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port_cnt++; /* Update port counter*/
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}
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}
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}
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fprintf(fp, ") begin\n");
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fprintf(fp, "\t\tassign %s_reg = %s;\n",
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output_port[0]->lib_name,
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input_port[0]->lib_name);
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fprintf(fp, "\tend else begin\n");
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fprintf(fp, "\t\tassign %s_reg = 1'bz;\n",
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output_port[0]->lib_name);
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fprintf(fp, "\tend\n");
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fprintf(fp, "end\n");
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fprintf(fp, "assign %s = %s_reg;\n",
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output_port[0]->lib_name,
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output_port[0]->lib_name);
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} else if (FALSE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf) {
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fprintf(fp, "assign %s = (%s === 1'bz)? $random : %s;\n",
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output_port[0]->lib_name,
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input_port[0]->lib_name,
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input_port[0]->lib_name);
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} else {
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assert (TRUE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf);
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fprintf(fp, "assign %s = (%s === 1'bz)? $random : ",
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output_port[0]->lib_name,
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input_port[0]->lib_name);
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/* depend on the stage, we may invert the output */
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if (1 == invbuf_spice_model->design_tech_info.buffer_info->tap_buf_level % 2) {
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fprintf(fp, "~");
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}
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fprintf(fp, "%s;\n",
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input_port[0]->lib_name);
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}
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n",
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__FILE__, __LINE__, invbuf_spice_model->name);
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exit(1);
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}
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/* Print timing info */
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dump_verilog_submodule_timing(fp, invbuf_spice_model);
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dump_verilog_submodule_signal_init(fp, invbuf_spice_model);
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fprintf(fp, "endmodule\n");
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fprintf(fp, "\n");
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/* Free */
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my_free(input_port);
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my_free(output_port);
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return;
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}
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/* Dump a module of pass-gate logic */
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static
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void dump_verilog_passgate_module(FILE* fp,
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t_spice_model* passgate_spice_model) {
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int iport;
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int num_input_port = 0;
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int num_output_port = 0;
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t_spice_model_port** input_port = NULL;
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t_spice_model_port** output_port = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find the input port, output port*/
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input_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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/* Make sure:
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* There is only 1 output port,
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* each size of which is 1
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*/
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assert(1 == num_output_port);
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assert(1 == output_port[0]->size);
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fprintf(fp, "//----- Verilog module for %s -----\n",
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passgate_spice_model->name);
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/* dump module body */
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fprintf(fp, "module %s (\n",
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passgate_spice_model->name);
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, passgate_spice_model, TRUE, FALSE, FALSE)) {
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fprintf(fp, ",\n");
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}
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/* Assign ports : depending on topology */
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switch (passgate_spice_model->design_tech_info.pass_gate_info->type) {
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case SPICE_MODEL_PASS_GATE_TRANSMISSION:
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/* Make sure:
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* There is only 3 input port (in, sel, selb),
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* each size of which is 1
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*/
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assert(3 == num_input_port);
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for (iport = 0; iport < num_input_port; iport++) {
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assert(1 == input_port[iport]->size);
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}
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/* Dump ports */
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fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name);
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fprintf(fp, "input [0:0] %s,\n", input_port[1]->lib_name);
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fprintf(fp, "input [0:0] %s,\n", input_port[2]->lib_name);
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fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name);
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fprintf(fp, ");\n");
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/* Finish dumping ports */
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break;
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case SPICE_MODEL_PASS_GATE_TRANSISTOR:
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/* Make sure:
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* There is only 2 input port (in, sel),
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* each size of which is 1
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*/
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assert(2 == num_input_port);
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for (iport = 0; iport < num_input_port; iport++) {
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assert(1 == input_port[iport]->size);
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}
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/* Dump ports */
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fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name);
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fprintf(fp, "input [0:0] %s,\n", input_port[1]->lib_name);
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fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name);
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fprintf(fp, ");\n");
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/* Finish dumping ports */
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n",
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__FILE__, __LINE__, passgate_spice_model->name);
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exit(1);
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}
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/* Dump logics */
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fprintf(fp, "assign %s = %s? %s : 1'bz;\n",
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output_port[0]->lib_name,
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input_port[1]->lib_name,
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input_port[0]->lib_name);
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/* Print timing info */
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dump_verilog_submodule_timing(fp, passgate_spice_model);
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/* Print signal initialization */
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dump_verilog_submodule_signal_init(fp, passgate_spice_model);
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fprintf(fp, "endmodule\n");
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fprintf(fp, "\n");
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/* Free */
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my_free(input_port);
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my_free(output_port);
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return;
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}
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/* Dump a module of pass-gate logic */
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static
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void dump_verilog_gate_module(FILE* fp,
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t_spice_model* gate_spice_model) {
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int iport, ipin, jport, jpin;
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int num_input_port = 0;
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int num_output_port = 0;
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t_spice_model_port** input_port = NULL;
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t_spice_model_port** output_port = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find the input port, output port*/
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input_port = find_spice_model_ports(gate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_port = find_spice_model_ports(gate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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/* Make sure:
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* There is only 1 output port,
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* each size of which is 1
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*/
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assert(1 == num_output_port);
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assert(1 == output_port[0]->size);
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assert(0 < num_input_port);
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fprintf(fp, "//----- Verilog module for %s -----\n",
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gate_spice_model->name);
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/* dump module body */
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fprintf(fp, "module %s (\n",
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gate_spice_model->name);
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, gate_spice_model, TRUE, FALSE, FALSE)) {
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fprintf(fp, ",\n");
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}
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/* Dump ports */
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for (iport = 0; iport < num_input_port; iport++) {
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fprintf(fp, "input [0:%d] %s,\n",
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input_port[iport]->size - 1, input_port[iport]->lib_name);
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}
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for (iport = 0; iport < num_output_port; iport++) {
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fprintf(fp, "output [0:%d] %s\n",
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output_port[iport]->size - 1, output_port[iport]->lib_name);
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}
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fprintf(fp, ");\n");
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/* Dump logics */
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switch (gate_spice_model->design_tech_info.gate_info->type) {
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case SPICE_MODEL_GATE_AND:
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for (iport = 0; iport < num_output_port; iport++) {
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for (ipin = 0; ipin < output_port[iport]->size; ipin++) {
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fprintf(fp, "assign %s[%d] = ",
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output_port[iport]->lib_name, ipin);
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for (jport = 0; jport < num_input_port; jport++) {
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for (jpin = 0; jpin < input_port[jport]->size; jpin++) {
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fprintf(fp, "%s[%d]",
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input_port[jport]->lib_name, jpin);
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if ((jport == num_input_port - 1) && (jpin == input_port[jport]->size - 1)) {
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continue; /* Stop output AND sign for the last element in the loop */
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}
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fprintf(fp, " & ");
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}
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}
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fprintf(fp, ";\n");
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}
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}
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break;
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case SPICE_MODEL_GATE_OR:
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for (iport = 0; iport < num_output_port; iport++) {
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for (ipin = 0; ipin < output_port[iport]->size; ipin++) {
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fprintf(fp, "assign %s[%d] = ",
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output_port[iport]->lib_name, ipin);
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for (jport = 0; jport < num_input_port; jport++) {
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for (jpin = 0; jpin < input_port[jport]->size; jpin++) {
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fprintf(fp, "%s[%d]",
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input_port[jport]->lib_name, jpin);
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if ((jport == num_input_port - 1) && (jpin == input_port[jport]->size - 1)) {
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continue; /* Stop output AND sign for the last element in the loop */
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}
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fprintf(fp, " | ");
|
||||
}
|
||||
}
|
||||
fprintf(fp, ";\n");
|
||||
}
|
||||
}
|
||||
break;
|
||||
case SPICE_MODEL_GATE_MUX2:
|
||||
/* Check on the port sequence and map */
|
||||
/* MUX2 should only have 1 output port with size 1 */
|
||||
if (1 != num_output_port) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d]) MUX2 circuit model must have only 1 output!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
} else if (1 != output_port[0]->size) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d]) Output size of a MUX2 circuit model must be 1!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
}
|
||||
/* MUX2 should only have 3 output port, each of which has a port size of 1 */
|
||||
if (3 != num_input_port) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d]) MUX2 circuit model must have only 3 input!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
} else {
|
||||
for (iport = 0; iport < num_input_port; iport++) {
|
||||
/* Bypass port size of 1 */
|
||||
if (1 == input_port[iport]->size) {
|
||||
continue;
|
||||
}
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d]) Input size MUX2 circuit model must be 1!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
/* Now, we output the logic of MUX2
|
||||
* IMPORTANT Restriction:
|
||||
* We always assum the first two inputs are data inputs
|
||||
* the third input is the select port
|
||||
*/
|
||||
fprintf(fp, "assign %s[%d] = %s[%d] ? %s[%d] : %s[%d];\n",
|
||||
output_port[0]->lib_name, 0,
|
||||
input_port[2]->lib_name, 0,
|
||||
input_port[0]->lib_name, 0,
|
||||
input_port[1]->lib_name, 0);
|
||||
break;
|
||||
default:
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n",
|
||||
__FILE__, __LINE__, gate_spice_model->name);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
|
||||
/* Print timing info */
|
||||
dump_verilog_submodule_timing(fp, gate_spice_model);
|
||||
|
||||
/* Print signal initialization */
|
||||
dump_verilog_submodule_signal_init(fp, gate_spice_model);
|
||||
|
||||
fprintf(fp, "endmodule\n");
|
||||
|
||||
fprintf(fp, "\n");
|
||||
|
||||
/* Free */
|
||||
my_free(input_port);
|
||||
my_free(output_port);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Dump Essential modules:
|
||||
* 1. inverters
|
||||
* 2. buffers
|
||||
* 3. pass-gate logics */
|
||||
static
|
||||
void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir,
|
||||
int num_spice_model,
|
||||
t_spice_model* spice_models) {
|
||||
int imodel;
|
||||
char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name);
|
||||
FILE* fp = NULL;
|
||||
|
||||
/* Create file */
|
||||
fp = fopen(verilog_name, "w");
|
||||
if (NULL == fp) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",
|
||||
__FILE__, __LINE__, essentials_verilog_file_name);
|
||||
exit(1);
|
||||
}
|
||||
dump_verilog_file_header(fp,"Essential gates");
|
||||
|
||||
verilog_include_defines_preproc_file(fp, verilog_dir);
|
||||
|
||||
/* Output essential models*/
|
||||
for (imodel = 0; imodel < num_spice_model; imodel++) {
|
||||
/* By pass user-defined modules */
|
||||
if (NULL != spice_models[imodel].verilog_netlist) {
|
||||
continue;
|
||||
}
|
||||
if (SPICE_MODEL_INVBUF == spice_models[imodel].type) {
|
||||
dump_verilog_invbuf_module(fp, &(spice_models[imodel]));
|
||||
}
|
||||
if (SPICE_MODEL_PASSGATE == spice_models[imodel].type) {
|
||||
dump_verilog_passgate_module(fp, &(spice_models[imodel]));
|
||||
}
|
||||
if (SPICE_MODEL_GATE == spice_models[imodel].type) {
|
||||
dump_verilog_gate_module(fp, &(spice_models[imodel]));
|
||||
}
|
||||
}
|
||||
|
||||
/* Close file handler*/
|
||||
fclose(fp);
|
||||
|
||||
/* Add fname to the linked list */
|
||||
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
|
||||
|
||||
/* Free */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Dump a CMOS MUX basis module */
|
||||
static
|
||||
void dump_verilog_cmos_mux_one_basis_module(FILE* fp,
|
||||
|
|
@ -4053,11 +3515,6 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
|
||||
/* 0. basic units: inverter, buffers and pass-gate logics, */
|
||||
vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n");
|
||||
/* To be removed when testing passed
|
||||
dump_verilog_submodule_essentials(verilog_dir, submodule_dir,
|
||||
Arch.spice->num_spice_model,
|
||||
Arch.spice->spice_models);
|
||||
*/
|
||||
print_verilog_submodule_essentials(std::string(verilog_dir),
|
||||
std::string(submodule_dir),
|
||||
Arch.spice->circuit_lib);
|
||||
|
|
|
|||
Loading…
Reference in New Issue