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added testbench CI

This commit is contained in:
Andrew Pond 2021-06-15 14:16:31 -06:00
parent 12b44e0eca
commit 3cfc42cdf9
8 changed files with 49 additions and 176 deletions
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176
openfpga_flow/benchmarks/config_loader/test_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2021 03:01:46 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "clock_divider.v"
`include "pulse_generator.v"
module test_top (
input sys_clk,
// Commented out i/o means it is floating and inaccessable to MPSoC
// input LUT5_OUT_1_pad,
input GPIO3_pad,
input GPIO0_pad,
input CC_SPYPAD_1_pad,
// input PERF_SPYPAD_0_pad,
// input LUT5_OUT_0_pad,
output RESET_pad,
output CLK_pad,
// input GPIO4_pad,
// input GPIO5_pad,
input GPIO2_pad,
input GPIO1_pad,
input LUT6_OUT_0_pad,
input TEST_EN_pad,
input LUT4_OUT_0_pad,
// input LUT4_OUT_1_pad,
// input LUT4_OUT_2_pad,
// input LUT4_OUT_3_pad,
input SC_HEAD_pad,
input CCFF_TAIL_pad,
input GPIO23_pad,
input GPIO11_pad,
// input GPIO21_pad,
input GPIO22_pad,
input GPIO20_pad,
input GPIO10_pad,
input GPIO8_pad,
input GPIO9_pad,
input GPIO18_pad,
input GPIO19_pad,
input GPIO6_pad,
input GPIO7_pad,
input CC_SPYPAD_0_pad,
input CC_SPYPAD_2_pad,
input SC_TAIL_pad,
input COUT_SPYPAD_0_pad,
output CCFF_HEAD_pad,
// input SHIFTREG_SPY_pad,
// input SC_SPYPAD_0_pad,
output PRESET_pad,
input GPIO12_pad,
input GPIO16_pad,
// input GPIO15_pad,
// input GPIO14_pad,
input GPIO13_pad,
output PROG_CLK_pad,
input GPIO17_pad,
output t0_pad,
output t1_pad,
output t2_pad,
input t3_pad,
output t0_is_output,
output t1_is_output,
output t2_is_output,
output t3_is_output
);
parameter RESET_LENGTH=10; // Start off test with 10 cycle reset
parameter TEST_START_CYCLE=11; // Start the test on cycle 11
// Local signals
wire logic_reset;
wire prog_reset;
wire logic_clk;
wire prog_clk;
wire ccff_head;
wire configuration_done;
// ****** GF12 Inputs / MPSoC Outputs ******
assign RESET_pad = logic_reset;
assign SC_HEAD_pad = 0;
assign CCFF_HEAD_pad = ccff_head;
assign PRESET_pad = prog_reset;
assign PROG_CLK_pad = prog_clk;
assign CLK_pad = logic_clk;
assign TEST_EN_pad = 0;
// *************************
// ******* MPSoC GPIO (4 inputs/outputs) *******
assign t0_pad = 0;
assign t1_pad = 0;
assign t2_pad = 0;
// assign start_signal = t3_pad;
assign t0_is_output = 1;
assign t1_is_output = 1;
assign t2_is_output = 1;
assign t3_is_output = 0;
// ********************************************
// ########################### CLOCKS ###########################
// CLK
// Divide pl_clk (50MHz) by 67108864 (2^26) times
clock_divider #(
.CLK_DIVIDER_SIZE(26)
) logic_clk_divider (
.clk_in(sys_clk),
.clk_out(logic_clk)
);
// ##############################################################
// ########################### RESETS ###########################
// RESET
// Logic reset will be enabled in the first 2 clock cycles
reset_generator #(
.INITIAL_VALUE(1),
.ACTIVE_CYCLES(100)
) logic_reset_generator(
.clk(sys_clk),
.pulse(logic_reset)
);
// ##############################################################
// ####################### CONFIGURATION #######################
// Configuration manager
configuration_manager config_manager (
.clk_in(sys_clk),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.configuration_done(configuration_done)
);
// ##############################################################
endmodule

0
openfpga_flow/benchmarks/config_loader/bitstream_loader.v → openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v
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0
openfpga_flow/benchmarks/config_loader/configuration_manager.v → openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v
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0
openfpga_flow/benchmarks/config_loader/clock_divider.v → openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
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0
openfpga_flow/benchmarks/config_loader/pulse_generator.v → openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
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0
openfpga_flow/benchmarks/config_loader/reset_generator.v → openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
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11
openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh Executable file
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#!/bin/bash
set -e
source openfpga.sh
PYTHON_EXEC=python3.8
###############################################
# OpenFPGA Shell with VPR8
##############################################
echo -e "Benchmark sweep tests";
run-task benchmark_sweep/signal_gen --debug --show_thread_logs

38
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
[SYNTHESIS_PARAM]
bench0_top = pulse_generator
# bench1_top = reset_generator
# bench2_top = clock_divider
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=