176 lines
4.2 KiB
Verilog
176 lines
4.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 03/11/2021 03:01:46 PM
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// Design Name:
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// Module Name: top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "clock_divider.v"
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`include "pulse_generator.v"
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module test_top (
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input sys_clk,
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// Commented out i/o means it is floating and inaccessable to MPSoC
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// input LUT5_OUT_1_pad,
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input GPIO3_pad,
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input GPIO0_pad,
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input CC_SPYPAD_1_pad,
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// input PERF_SPYPAD_0_pad,
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// input LUT5_OUT_0_pad,
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output RESET_pad,
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output CLK_pad,
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// input GPIO4_pad,
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// input GPIO5_pad,
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input GPIO2_pad,
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input GPIO1_pad,
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input LUT6_OUT_0_pad,
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input TEST_EN_pad,
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input LUT4_OUT_0_pad,
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// input LUT4_OUT_1_pad,
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// input LUT4_OUT_2_pad,
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// input LUT4_OUT_3_pad,
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input SC_HEAD_pad,
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input CCFF_TAIL_pad,
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input GPIO23_pad,
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input GPIO11_pad,
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// input GPIO21_pad,
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input GPIO22_pad,
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input GPIO20_pad,
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input GPIO10_pad,
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input GPIO8_pad,
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input GPIO9_pad,
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input GPIO18_pad,
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input GPIO19_pad,
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input GPIO6_pad,
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input GPIO7_pad,
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input CC_SPYPAD_0_pad,
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input CC_SPYPAD_2_pad,
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input SC_TAIL_pad,
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input COUT_SPYPAD_0_pad,
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output CCFF_HEAD_pad,
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// input SHIFTREG_SPY_pad,
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// input SC_SPYPAD_0_pad,
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output PRESET_pad,
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input GPIO12_pad,
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input GPIO16_pad,
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// input GPIO15_pad,
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// input GPIO14_pad,
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input GPIO13_pad,
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output PROG_CLK_pad,
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input GPIO17_pad,
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output t0_pad,
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output t1_pad,
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output t2_pad,
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input t3_pad,
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output t0_is_output,
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output t1_is_output,
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output t2_is_output,
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output t3_is_output
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);
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parameter RESET_LENGTH=10; // Start off test with 10 cycle reset
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parameter TEST_START_CYCLE=11; // Start the test on cycle 11
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// Local signals
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wire logic_reset;
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wire prog_reset;
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wire logic_clk;
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wire prog_clk;
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wire ccff_head;
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wire configuration_done;
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// ****** GF12 Inputs / MPSoC Outputs ******
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assign RESET_pad = logic_reset;
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assign SC_HEAD_pad = 0;
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assign CCFF_HEAD_pad = ccff_head;
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assign PRESET_pad = prog_reset;
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assign PROG_CLK_pad = prog_clk;
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assign CLK_pad = logic_clk;
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assign TEST_EN_pad = 0;
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// *************************
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// ******* MPSoC GPIO (4 inputs/outputs) *******
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assign t0_pad = 0;
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assign t1_pad = 0;
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assign t2_pad = 0;
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// assign start_signal = t3_pad;
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assign t0_is_output = 1;
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assign t1_is_output = 1;
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assign t2_is_output = 1;
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assign t3_is_output = 0;
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// ********************************************
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// ########################### CLOCKS ###########################
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// CLK
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// Divide pl_clk (50MHz) by 67108864 (2^26) times
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clock_divider #(
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.CLK_DIVIDER_SIZE(26)
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) logic_clk_divider (
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.clk_in(sys_clk),
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.clk_out(logic_clk)
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);
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// ##############################################################
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// ########################### RESETS ###########################
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// RESET
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// Logic reset will be enabled in the first 2 clock cycles
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reset_generator #(
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.INITIAL_VALUE(1),
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.ACTIVE_CYCLES(100)
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) logic_reset_generator(
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.clk(sys_clk),
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.pulse(logic_reset)
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);
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// ##############################################################
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// ####################### CONFIGURATION #######################
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// Configuration manager
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configuration_manager config_manager (
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.clk_in(sys_clk),
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.prog_reset(prog_reset),
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.prog_clk(prog_clk),
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.ccff_head(ccff_head),
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.configuration_done(configuration_done)
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);
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// ##############################################################
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endmodule |