bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm

openfpga/src/fabric/build_top_module_memory.cpp

@@ -2,6 +2,8 @@
  * This file includes functions that are used to organize memories 
  * in the top module of FPGA fabric
  *******************************************************************/
+#include <cmath>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
@@ -652,7 +654,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
       /* Find the BL decoder data index: 
        * It should be the residual when divided by the number of BLs
        */
-      size_t bl_pin_id = cur_bl_index / num_bls;
+      size_t bl_pin_id = std::floor(cur_bl_index / num_bls);
 
       /* Create net */
       ModuleNetId net = create_module_source_pin_net(module_manager, top_module,

openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp

@@ -2,6 +2,7 @@
  * This file includes functions to build fabric dependent bitstream
  *******************************************************************/
 #include <string>
+#include <cmath>
 #include <algorithm>
 
 /* Headers from vtrutil library */
@@ -115,6 +116,13 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
       num_configurable_children -= 2;
     }
 
+    /* Early exit if there is no configurable children */
+    if (0 == num_configurable_children) {
+      /* Ensure that there should be no configuration bits in the parent block */
+      VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+      return;
+    }
+
     for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
       ModuleId child_module = configurable_children[child_id]; 
       size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
@@ -137,6 +145,8 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
     }
     /* Ensure that there should be no configuration bits in the parent block */
     VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+
+    return;
   }
 
   /* Note that, reach here, it means that this is a leaf node. 
@@ -147,7 +157,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
     FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit);
   
     /* Find BL address */
-    size_t cur_bl_index = cur_mem_index / num_bls;
+    size_t cur_bl_index = std::floor(cur_mem_index / num_bls);
     std::vector<size_t> bl_addr_bits_vec = itobin_vec(cur_bl_index, bl_addr_size);
 
     /* Find WL address */

openfpga/src/fpga_verilog/verilog_decoders.cpp

@@ -503,7 +503,9 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
   /* Different from MUX decoder, we assign default values which is all zero */
   fp << "\t\t\t" << "default"; 
   fp << " : ";
-  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); 
+  fp << " = ";
+  fp << high_res_str;
   fp << ";" << std::endl;
 
   fp << "\t\t" << "endcase" << std::endl;
@@ -511,7 +513,9 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
 
   /* If enable is not active, we should give all zero */
   fp << "\t" << "else begin" << std::endl;
-  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); 
+  fp << " = ";
+  fp << high_res_str;
   fp << ";" << std::endl;
   fp << "\t" << "end" << std::endl;
   

openfpga/src/fpga_verilog/verilog_writer_utils.cpp

@@ -517,16 +517,18 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
     if (&port == &ports[0]) {
       continue;
     } 
-    /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
+    /* Identify if the port name can be potentially merged: 
-    bool merged = false;
+     * if the port can be merged to the last port in the list, it may be merged
-    for (auto& merged_port : merged_ports) {
+     */
-      if (false == port.mergeable(merged_port)) {
+    if (false == port.mergeable(merged_ports.back())) {
-        /* Unable to merge, Go to next */
+      /* Unable to merge, add the port to merged port list */
+      merged_ports.push_back(port);
       continue;
     }
     /* May be merged, check LSB of port and MSB of merged_port */
-      if (merged_port.get_msb() + 1 != port.get_lsb()) {
+    if (merged_ports.back().get_msb() + 1 != port.get_lsb()) {
-        /* Unable to merge, Go to next */
+      /* Unable to merge, add the port to merged port list */
+      merged_ports.push_back(port);
       continue;
     } 
     /* Reach here, we should merge the ports,
@@ -534,14 +536,8 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
      * MSB of merged_port will be updated 
      * to the MSB of port 
      */
-      merged_port.set_msb(port.get_msb());
+    BasicPort& port_to_merge = merged_ports.back();
-      merged = true;
+    port_to_merge.set_msb(port.get_msb());
-      break;
-    }
-    if (false == merged) {
-      /* Unable to merge, add the port to merged port list */
-      merged_ports.push_back(port);
-    }
   }
 
   return merged_ports;