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copy yosys output file in case power analysis setting is off

This commit is contained in:
Tarachand Pagarani 2021-02-15 02:36:02 -08:00
parent 45e8baf98f
commit 3a587f663a
1 changed files with 2 additions and 0 deletions
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2
openfpga_flow/scripts/run_fpga_flow.py
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@ -261,6 +261,8 @@ def main():
run_ace2() run_ace2()
run_pro_blif_3arg() run_pro_blif_3arg()
run_rewrite_verilog() run_rewrite_verilog()
else:
shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
if (args.fpga_flow == "vpr_blif"): if (args.fpga_flow == "vpr_blif"):
collect_files_for_vpr() collect_files_for_vpr()
logger.info("Runing OpenFPGA Shell Engine ") logger.info("Runing OpenFPGA Shell Engine ")