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[Script] Skip analysis SDC in multi-clock benchmarks

This commit is contained in:
tangxifan 2022-03-20 10:29:27 +08:00
parent 408652e677
commit 38a81e840e
1 changed files with 3 additions and 1 deletions
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4
openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
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@ -72,7 +72,9 @@ write_pnr_sdc --file ./SDC
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric # Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis # TODO: Currently analysis SDC does not support multiple clocks due to
# - Missing information about which I/Os are constrained by which clock
#write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA # Finish and exit OpenFPGA
exit exit